Adaptive matched digital filter

Claim 2

An electronic filter, comprising, means receiving an electronic noise plus signal waveform for sampling said waveform at periodic intervals with the amplitude of each waveform sample expressed in a binary code, a digital filter receiving the binary waveform samples at an input and forming a filtered binary signal at an output, said filter having a transfer function that is controllable by application of a plurality of binary constants thereto, and means receiving said input binary samples for automatically generating said transfer function controlling filter binary constants and continuously conforming said constants to changes in said noise plus signal waveform.

Claim 3

Apparatus according to claim 1 wherein said digital filter includes a transversal type linear filter.

Claim 4

Apparatus according to claim 1 where said means for generating said filter constants includes a general purpose digital computer.

Claim 5

Apparatus according to claim 3 wherein said digital computer is preprogrammed with a desired signal to be extracted from said noise plus signal waveform, said preprogrammed desired signal being used in determining said filter constants.

Claim 6

An electronic apparatus for filtering a time varying electronic input signal that includes a desired signal plus undesired noise, comprising, an analog-to-digital converter which samples said input signal at periodic intervals and produces a serial output of samples, each sample including a parallel binary word representation of the magnitude of the sample, a common clock pulse source connected to said analog-to-digital converter for controlling the periodic interval at which said samples are made, a delay line including a plurality of stages connected to said analog-to-digital converter to receive the binary samples, said common clock source connected to said delay line for moving the individual binary word samples along said delay line through one stage at each clock pulse, a digital multiplier associated with each delay line stage, each multiplier having two binary data inputs and an output which generates a binary multiple of the two inputs, one of said inputs of each multiplier connected to receive the sample at its associated stage of the delay line and the other of each input of each multiplier connected to receive a distinct constant in the form of a binary word, the value of the binary word constants determining the transfer function of the electronic filter, means receiving said binary samples at the output of the analog-to-digital converter for automatically determining and setting the individual binary word constants at each digital multiplier whereby the transfer function of the electronic filter is set in response to the input signal, a digital summer receiving the digital outputs of each of the multipliers and forming a common digital output, and a digital-to-analog converter connected to said summer which forms the filter output.

Claim 7

An electronic apparatus for filtering a time varying electronic input signal that includes a desired signal plus undesired noise, comprising, an analog-to-digital converter which samples said input signal at periodic intervals and produces a serial output of samples, each sample including a parallel binary word representation of the magnitude of the sample, a common clock pulse source connected to said analog-to-digital converter for controlling the periodic interval at which said samples are made, a delay line including a plurality of stages connected to said analog-to-digital converter to receive the binary samples, said common clock source connected to said delay line for moving the individual binary word samples along said delay line through one stage at each clock pulse, a digital multiplier associated with each delay line stage, each multiplier having two binary data inputs and an output which generates a binary multiple of the two inputs, one of said inputs of each multiplier connected to receive the sample at its associated stage of the delay line and the other of each input of each multiplier connected to receive a distinct constant in the form of a binary word, the value of the binary word constants determining the transfer function of the electronic filter, means receiving said binary samples at the output of the analog-to-digital converter for automatically determining and setting the individual binary word constants at each digital multiplier whereby the transfer function of the electronic filter is set in response to the input signal, a digital summer receiving the digital outputs of each of the multipliers and forming a common digital output, and a digital-to-analog converter connected to said summer which forms the filter output.

Claim 8

Apparatus according to claim 5 wherein each stage of said delay line includes a digital shift register.

Claim 9

Apparatus according to claim 5 wherein said means for determining said multiplier constants includes a digital computer.

Claim 10

Apparatus according to claim 7 that additionally comprises a shift register at the input of said computer for receiving a series of binary input signal samples from said analog-to-digital converter and feeding said samples into the computer at a rate that is less than the rate of said common clock source.

Claim 17

An adaptive digital filter, comprising: a digital delay line having a plurality of serially connected stages from an input, a digital multiplier associated with each delay line stage, each multiplier characterized by two binary data inputs and an output that delivers a binary multiple of the two inputs, one of said inputs of each multiplier being connected to receive the binary content at its associated stage of the delay line and the other of each input of each multiplier connected to receive a distinct binary constant, whereby the value of all the binary constants determines the transfer function of the adaptive digital filter, a general purpose digital computer connected to said delay line input for calculating and setting values of said binary constants from at least some of the binary data that appears at the delay line input, said computer having a plurality of outputs with one output connected to each of said other inputs of the multipliers, and a digital summer receiving the digital outputs of all the multipliers and forming a filtered digital output.

Claim 18

An adaptive digital filter, comprising: a digital delay line having a plurality of serially connected stages from an input, a digital multiplier associated with each delay line stage, each multiplier characterized by two binary data inputs and an output that delivers a binary multiple of the two inputs, one of said inputs of each multiplier being connected to receive the binary content at its associated stage of the delay line and the other of each input of each multiplier connected to receive a distinct binary constant, whereby the value of all the binary constants determines the transfer function of the adaptive digital filter, a general purpose digital computer connected to said delay line input for calculating and setting values of said binary constants from at least some of the binary data that appears at the delay line input, said computer having a plurality of outputs with one output connected to each of said other inputs of the multipliers, and a digital summer receiving the digital outputs of all the multipliers and forming a filtered digital output.

Claim 19

The adaptive digital filter of claim 12 wherein said general purpose digital computer is connected to periodically receive a plurality of binary samples of a signal plus noise at said input, the number of said samples being several times the number of said digital multiplier, said computer additionally being connected to first compute the auto-correlation of said plurality of binary samples and then secondly to solve a number of simultaneous linear equations equal to the number of said digital multipliers and which each relate the auto-correlations of said samples with said binary constants, whereby said binary constants are determined.

Claim 20

The adaptive digital filter of claim 12 wherein each of said digital delay line stages includes a parallel eight bit storage element and wherein there are sixty-four of said digital multipliers.