Decision-directed adapted equalizer circuit

Claim 2

A circuit for reducing the effects of intersymbol interference and additive noise in the transmission of digital data comprising: first data storage means having a number of series connected delay elements, each delay element being operable to store a particular symbol of a data sequence; a first plurality of multiplier means, each multiplier means having an input connection to a separate delay element of said first data storage means and being operable to multiply the particular symbol of the first data sequence stored in its associated delay element by a predetermined value to form a resulting product signal; second data storage means having a number of series connected delay elements and being operable to store the symbols of a second data sequence in the delay elements of said second storage means; a second plurality of multiplier means, each having an input connection to a separate delay element of said second data storage means and being operable to multiply the symbols of the second data sequence stored in its associated delay element by a predetermined value to form a resulting product signal; quantizer means having an input terminal and an output terminal, said output terminal being connected to said second data storage means; first summation means connected between each multiplier means of said first and second plurality of multiplier means and the input terminal of said quantizer means and being operable to sum the product signals from each of said multiplier means to produce an estimate signal of the symbol of the first data sequence stored in a predetermined storage element of said first data storage means, said quantizer means being operative to quantize the estimate signal from said first summation means into a predetermined number of signal levels; and feedback means having input connections from said first summation means and said quantizer means and an output connection to each multiplier means of said first and second plurality of multiplier means, said feedback means being operable to compare the estimate signal from said first summation means with the quantized estimate signal and to produce an error signal which adjusts the gain of each multiplier means to thereby set the predetermined value of each of said multiplier means.

Claim 3

A circuit for reducing the effect of intersymbol interference and additive noise in the transmission of digital data comprising: first delay line filter means having an input terminal, an output terminal, a plurality of series-connected delay elements of predetermined delay value connected between said input and output terminals and a plurality of taps, each tap being connected to a separate juncture of two of said delay elements, said first delay line filter being operative to store said digital data having intersymbol interference; first summation means; first plurality of multiplier means, each of said multiplier means being connected between a separate one of said plurality of taps of said first delay line filter and said first summation means and each of said multiplier means being operative to multiply a signal stored in its associated delay element by a predetermined value; second delay line filter means having an input terminal, a plurality of series-connected delay elements of predetermined delay value and a plurality of taps, each of said taps being connected to a separate juncture of two of said delay elements of said second delay line filter; second plurality of multiplier means, each being connected between a separate one of said plurality of taps of said second delay line filter means and said first summation means and each of said multiplier circuits being operative to multiply a signal stored in its associated delay element by a predeteRmined value; said first summation means being operative to sum the output signals from each of the multiplier means of said first and second plurality of multiplier means to form an estimate of the signal stored in the last delay element of said first delay line filter means; quantizer means having an input connection to said first summation means and an output connection to the input terminal of said second delay line filter connection, said quantizer means being operative to quantize the estimate signal from said first summation means; and feedback means having input connections from said first summation means and said quantizer means and an output connection to each of said multiplier means of said first and second plurality of multiplier means, said feedback means being operative to generate an error signal proportional to the difference between the estimate signal from said first summation means and the quantized signal from said quantizer means, each of said multiplier means being operative to adjust its gain in response to the error signal from said feedback means.

Claim 4

A circuit for reducing the effect of intersymbol interference and additive noise in the transmission of digital data comprising: first delay line filter means having an input terminal, an output terminal, a plurality of series-connected delay elements of predetermined delay value connected between said input and output terminals and a plurality of taps, each tap being connected to a separate juncture of two of said delay elements, said first delay line filter being operative to store said digital data having intersymbol interference; first summation means; first plurality of multiplier means, each of said multiplier means being connected between a separate one of said plurality of taps of said first delay line filter and said first summation means and each of said multiplier means being operative to multiply a signal stored in its associated delay element by a predetermined value; second delay line filter means having an input terminal, a plurality of series-connected delay elements of predetermined delay value and a plurality of taps, each of said taps being connected to a separate juncture of two of said delay elements of said second delay line filter; second plurality of multiplier means, each being connected between a separate one of said plurality of taps of said second delay line filter means and said first summation means and each of said multiplier circuits being operative to multiply a signal stored in its associated delay element by a predeteRmined value; said first summation means being operative to sum the output signals from each of the multiplier means of said first and second plurality of multiplier means to form an estimate of the signal stored in the last delay element of said first delay line filter means; quantizer means having an input connection to said first summation means and an output connection to the input terminal of said second delay line filter connection, said quantizer means being operative to quantize the estimate signal from said first summation means; and feedback means having input connections from said first summation means and said quantizer means and an output connection to each of said multiplier means of said first and second plurality of multiplier means, said feedback means being operative to generate an error signal proportional to the difference between the estimate signal from said first summation means and the quantized signal from said quantizer means, each of said multiplier means being operative to adjust its gain in response to the error signal from said feedback means.

Claim 5

A circuit for reducing the effect of intersymbol interference and additive noise according to claim 2 wherein each of said multiplier means includes: a first multiplier circuit having a first input connection from its associated tap and a second input connection from the output connection of said feedback means, said first multiplier circuit being operative to obtain the product of the signal stored in its associated delay element by the error signal from said feedback means; a second summation means connected to said first multiplier circuit and being operative to add the product obtained from said first multiplier circuit to the product from the previous signal to thereby generate said predetermined value; and a second multiplier circuit having a first input connection from its associated tap and a second input connection from said second summation means and being operative to provide the resultant product signal to said first summation means.

Claim 6

A circuit for reducing the effect of intersymbol interference according to claim 3 wherein said feedback means includes: third summation means having a first input connection from said first summation means and a second input connection from said quantizer means, and being operative to compare the estimate signal and the quantizer estimate signal to obtain a difference signal; and a third multiplier circuit having an input connection from said third summation means and an output connection to each of said multiplier means, said third multiplier circuit being operative to multiply the difference signal from said third summation means by a predetermined factor to thereby produce said error signal to adjust the predetermined value of gain of each of said multiplier means.