Nonrecursive digital filter apparatus employing delayedadd configuration

Claim 2

Apparatus for algebraically combining a predetermined number of weighted signal samples from each of (K) sources, said samples being applied to said apparatus in a predetermined sequence, there being a predetermined interval of time between the application of any two of said samples, comprising: an ordered plurality of serially connected multistage shift registers each producing a series of output signal samples each of which is (K+1) samples earlier in said sequence of applied signal samples than the output signal sample concurrently produced by the preceding one of said shift registers; a plurality of multipliers, each solely associated with one of said shift registers, each producing a series of output signal words, each of which is the product of one of said output signal samples of said associated shift register and a predetermined filter coefficient; a plurality of adders, each solely associated with one of said shift registers, for adding each of said output words of said multiplier associated with said associated shift register and an applied delayed partial sum word to produce a partial sum output signal word; a plurality of partial sum output word delay units, each solely associated with one of said shift registers, for delaying each of said partial sum output words of said adder associated with said shift register for said predetermined interval of time between samples; and means for applying each of the delayed partial sum output words produced by each of said partial sum delay units to the adder associated with the next of said ordered shift registers.

Claim 3

Nonrecursive digital filtering apparatus for performing predetermined arithmetic operations on sequentially applied digitally coded signal samples from each of K sources, there being a predetermined interval of time between the application of any two of said samples, comprising: a plurality of serially connected filter modules, each module further comprising: a sample delay unit for delaying each sample applied to it by the time required for the application of (K+1) samples to said filter; a multiplier for multiplying each of said delayed samples by a predetermined filter coefficient; an adder for adding each of said multiplied samples to an applied delayed partial sum signal word to produce a partial sum output signal word; and a partial sum delay unit for delaying each of said partial sum output signal words by said interval of time between applied samples; means for applying said delayed samples of each of said filter modules to said sample delay unit of the next module; and means for applying said delayed partial sum words of each of said filter modules to said adder of said next filter module.

Claim 4

Nonrecursive digital filtering apparatus for performing predetermined arithmetic operations on sequentially applied digitally coded signal samples from each of K sources, there being a predetermined interval of time between the application of any two of said samples, comprising: a plurality of serially connected filter modules, each module further comprising: a sample delay unit for delaying each sample applied to it by the time required for the application of (K+1) samples to said filter; a multiplier for multiplying each of said delayed samples by a predetermined filter coefficient; an adder for adding each of said multiplied samples to an applied delayed partial sum signal word to produce a partial sum output signal word; and a partial sum delay unit for delaying each of said partial sum output signal words by said interval of time between applied samples; means for applying said delayed samples of each of said filter modules to said sample delay unit of the next module; and means for applying said delayed partial sum words of each of said filter modules to said adder of said next filter module.

Claim 5

Nonrecursive digital filter apparatus including a plurality of serially connected means for sequentially delaying digitally coded signal samples from each of a plurality of sources applied to the filter at a predetermined rate, the reciprocal of which is the filter cycle interval, and means for multiplying each of the applied and delayed samples by a predetermined filter coefficient wherein the improvement comprises: an additional filter cycle interval of delay associated with each of said serially connected means; a plurality of serially interconnected adders for adding said multiplied samples to produce a digitally coded output signal; and a plurality of partial sum delay units, one of which is included in each adder interconnection, for delaying the output signal of each adder by one sample period before applying it to the next of said adders.

Claim 6

Nonrecursive digital filter apparatus including a plurality of serially connected means for sequentially delaying digitally coded signal samples from each of a plurality of sources applied to the filter at a predetermined rate, the reciprocal of which is the filter cycle interval, and means for multiplying each of the applied and delayed samples by a predetermined filter coefficient wherein the improvement comprises: an additional filter cycle interval of delay associated with each of said serially connected means; a plurality of serially interconnected adders for adding said multiplied samples to produce a digitally coded output signal; and a plurality of partial sum delay units, one of which is included in each adder interconnection, for delaying the output signal of each adder by one sample period before applying it to the next of said adders.

Claim 7

A nonrecursive digital filter for processing sequentially applied digitally coded signal samples from each of (K) signal sources comprising: a plurality of shift registers connected in series forming an ordered set of shift registers, each of said shift registers having capacity for the simultaneous storage of (K + 1) signal samples; a plurality of multiplier devices, each responsive to the output signal of one of said shift registers for generating an output signal representative of the product of the quantity represented by said shift register output signal and a filter coefficient quantity; a plurality of adder devices and storage devices connected in alternating series, said adders in said alteRnating series forming an ordered set of adder devices corresponding to said ordered set of shift registers, each one of said adder devices being responsive to said output signal of the one of said multipliers associated with the corresponding shift register in said ordered set of shift registers for generating an output signal representative of the sum of said multiplier output signal and the output signal of the preceding storage device in said alternating series, each of said storage devices having capacity for the storage of one of said signal sums; and means responsive to the output signal of one of said adders for providing a filtered output signal.

Claim 8

A nonrecursive digital filter for processing sequentially applied digitally coded signal samples from each of (K) signal sources comprising: a plurality of shift registers connected in series forming an ordered set of shift registers, each of said shift registers having capacity for the simultaneous storage of (K + 1) signal samples; a plurality of multiplier devices, each responsive to the output signal of one of said shift registers for generating an output signal representative of the product of the quantity represented by said shift register output signal and a filter coefficient quantity; a plurality of adder devices and storage devices connected in alternating series, said adders in said alteRnating series forming an ordered set of adder devices corresponding to said ordered set of shift registers, each one of said adder devices being responsive to said output signal of the one of said multipliers associated with the corresponding shift register in said ordered set of shift registers for generating an output signal representative of the sum of said multiplier output signal and the output signal of the preceding storage device in said alternating series, each of said storage devices having capacity for the storage of one of said signal sums; and means responsive to the output signal of one of said adders for providing a filtered output signal.

Claim 9

Nonrecursive digital filtering apparatus for processing digitally coded signal samples from each of K sources, said samples being sequentially applied at a predetermined rate the reciprocal of which is the filter cycle interval, comprising: a tapped delay line for delaying said sequentially applied samples, said delay line having a plurality of taps spaced apart on said delay line by (K + 1) sample periods; a plurality of multipliers, one of which is associated with each of said taps, for multiplying the samples applied to each of said taps by predetermined filter coefficients; a plurality of adders, one of which is associated with each of said taps, for adding the multiplied samples produced by the multiplier associated with each of said taps and a series of applied delayed partial sum words to produce a series of partial sum output words; a plurality of partial sum delay units, one of which is associated with each of said taps, for delaying said partial sum output words produced by the adder associated with each of said taps by one sample period to produce a series of delayed partial sum output words; and means for applying said delayed partial sum output words produced by each of said partial sum delay units to the adder associated with the next of said taps.

Claim 10

Nonrecursive digital filtering apparatus for processing digitally coded signal samples from each of K sources, said samples being sequentially applied at a predetermined rate the reciprocal of which is the filter cycle interval, comprising: a tapped delay line for delaying said sequentially applied samples, said delay line having a plurality of taps spaced apart on said delay line by (K + 1) sample periods; a plurality of multipliers, one of which is associated with each of said taps, for multiplying the samples applied to each of said taps by predetermined filter coefficients; a plurality of adders, one of which is associated with each of said taps, for adding the multiplied samples produced by the multiplier associated with each of said taps and a series of applied delayed partial sum words to produce a series of partial sum output words; a plurality of partial sum delay units, one of which is associated with each of said taps, for delaying said partial sum output words produced by the adder associated with each of said taps by one sample period to produce a series of delayed partial sum output words; and means for applying said delayed partial sum output words produced by each of said partial sum delay units to the adder associated with the next of said taps.

Claim 11

Nonrecursive digital filtering apparatus for convolving sequentially applied digitally coded signal samples from each of (K) sources with a symmetrical set of N + 1 time domain filter coefficients, said samples being applied to said apparatus at a predetermined rate, the reciprocal of which is the filter cycle interval, comprising: a tapped delay line for delaying said sequentially applied samples, said delay line having N+1 taps each of those up to and including the center tap being separated from the preceding tap by a (K+1) sample period delay and each of the remaining taps being separated from the preceding tap by a (K-1) sample period delay; a first plurality of adders, one of which is associated with each pair of taps which are symmetrically located along said delay line with respect to said center tap for pairwise addition of said samples applied to said symmetrical pair of taps; a plurality of multipliers, one of which is associated with each of said first plurality of adders for multiplying said added samples by a predetermined filter coefficient; a center tap multiplier associated with said center tap for multiplying samples applied to said center tap by a predetermined filter coefficient; a second plurality of adders, one of which is associated with each of said multipliers for adding said multiplied samples to a series of applied delayed partial sum signal words to produce a series of output partial sum signal words; a plurality of partial sum delay units, one of which is associated with each of said second plurality of adders for delaying each word in said series of output sum words by one sample period to produce a series of delayed partial sum words; and means for applying said series of delayed partial sum words produced by each of said partial sum delay units associated with one of said pairs of symmetrical taps to the one of said second plurality of adders associated with said pair of symmetrical taps next cloSet to said center tap and for applying said series of delayed partial sum words produced by said partial sum delay unit associated with said symmetrical taps adjacent to said center tap to said one of said second plurality of adders associated with said center tap.

Claim 12

Nonrecursive digital filtering apparatus for convolving sequentially applied digitally coded signal samples from each of (K) sources with a symmetrical set of N + 1 time domain filter coefficients, said samples being applied to said apparatus at a predetermined rate, the reciprocal of which is the filter cycle interval, comprising: a tapped delay line for delaying said sequentially applied samples, said delay line having N+1 taps each of those up to and including the center tap being separated from the preceding tap by a (K+1) sample period delay and each of the remaining taps being separated from the preceding tap by a (K-1) sample period delay; a first plurality of adders, one of which is associated with each pair of taps which are symmetrically located along said delay line with respect to said center tap for pairwise addition of said samples applied to said symmetrical pair of taps; a plurality of multipliers, one of which is associated with each of said first plurality of adders for multiplying said added samples by a predetermined filter coefficient; a center tap multiplier associated with said center tap for multiplying samples applied to said center tap by a predetermined filter coefficient; a second plurality of adders, one of which is associated with each of said multipliers for adding said multiplied samples to a series of applied delayed partial sum signal words to produce a series of output partial sum signal words; a plurality of partial sum delay units, one of which is associated with each of said second plurality of adders for delaying each word in said series of output sum words by one sample period to produce a series of delayed partial sum words; and means for applying said series of delayed partial sum words produced by each of said partial sum delay units associated with one of said pairs of symmetrical taps to the one of said second plurality of adders associated with said pair of symmetrical taps next cloSet to said center tap and for applying said series of delayed partial sum words produced by said partial sum delay unit associated with said symmetrical taps adjacent to said center tap to said one of said second plurality of adders associated with said center tap.

Claim 13

Nonrecursive digital filtering apparatus including at least two nonrecursive filter subsections for processing sequentially applied digitally coded signal samples from each of (K) sources, said samples being applied to said apparatus at a predetermined rate the reciprocal of which is the filter cycle interval, wherein the improvement comprises: means for delaying for (K+1) filter cycle intervals said samples delayed by each of said filter subsections before applying said samples to the next of said filter subsections; and means for delaying the filtered output words produced by each of said filter subsections for one filter cycle interval before summation of said output words with the output words produced by the next of said filter subsections.

Claim 14

Nonrecursive digital filtering apparatus including at least two nonrecursive filter subsections for processing sequentially applied digitally coded signal samples from each of (K) sources, said samples being applied to said apparatus at a predetermined rate the reciprocal of which is the filter cycle interval, wherein the improvement comprises: means for delaying for (K+1) filter cycle intervals said samples delayed by each of said filter subsections before applying said samples to the next of said filter subsections; and means for delaying the filtered output words produced by each of said filter subsections for one filter cycle interval before summation of said output words with the output words produced by the next of said filter subsections.

Claim 15

Nonrecursive digital filtering apparatus for performing predetermined arithmetic operations on sequentially applied digitally coded signal samples from each of (K) sources comprising: a plurality of serially interconnected shift registers for successively delaying said applied signal samples, at least one of said shift registers having capacity for the simultaneous storage of (K+1) signal samples, the remainder of said shift registers having capacity for the simultaneous storage of (K) signal samples, each group of said K-sample shift registers which are interconnected comprising one of a plurality of subsets of said shift registers; a plurality of multipliers, one of which is connected to each of said shift register interconnections, for producing a plurality of digitally coded product words each of which is representative of the product of one of said delayed signal samples and a predetermined filter coefficient; a plurality of partial sum delay units, each of said delay units being associated with one of said subsets of K-sample shift registers and each having capacity for the storage of one applied digitally coded partial sum word; a plurality of adder means, one of which is associated with each of said subsets of K-sample shift registers for applying to the one of said partial sum delay units associated with said subset of K-sample delay units a digitally coded partial sum word representative of an algebraic combination of said product words produced by those of said multipliers connected to each of said interconnections of each of said K-sample shift registers comprising said subset and said partial sum word stored in said partial sum delay unit associated with the preceding subset of K-sample delay units; and means responsive to the output signal of one of said adders for providing a filtered output signal.

Claim 16

Nonrecursive digital filtering apparatus for performing predetermined arithmetic operations on sequentially applied digitally coded signal samples from each of (K) sources comprising: a plurality of serially interconnected shift registers for successively delaying said applied signal samples, at least one of said shift registers having capacity for the simultaneous storage of (K+1) signal samples, the remainder of said shift registers having capacity for the simultaneous storage of (K) signal samples, each group of said K-sample shift registers which are interconnected comprising one of a plurality of subsets of said shift registers; a plurality of multipliers, one of which is connected to each of said shift register interconnections, for producing a plurality of digitally coded product words each of which is representative of the product of one of said delayed signal samples and a predetermined filter coefficient; a plurality of partial sum delay units, each of said delay units being associated with one of said subsets of K-sample shift registers and each having capacity for the storage of one applied digitally coded partial sum word; a plurality of adder means, one of which is associated with each of said subsets of K-sample shift registers for applying to the one of said partial sum delay units associated with said subset of K-sample delay units a digitally coded partial sum word representative of an algebraic combination of said product words produced by those of said multipliers connected to each of said interconnections of each of said K-sample shift registers comprising said subset and said partial sum word stored in said partial sum delay unit associated with the preceding subset of K-sample delay units; and means responsive to the output signal of one of said adders for providing a filtered output signal.