Patent US3849726A successfully refreshed from Google Patents.
US3849726A
Expired / Lapsed
US
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Universal programmable digital testing interface line
Assignee: SP-MICROWAVE Inc
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Filing: 1974-01-28
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Granted: 1974-11-19
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Expires: 1994-01-28
Abstract
Abstract A programmable interface line for use with automatic digital test equipment includes a line driver in which first and second output transistors are driven into saturation so as to couple the output line directly to first or second voltage sources respectively in order to provide a stimulus signal representative of the two binary levels. The circuit is programmed to receive response signals by cutting off the output transistors and diverting the response signals to a comparator in which the response signals are compared with reference signals during a specified time interval. A loading circuit includes switches for independently coupling load impedances to a voltage reference so as to evaluate a variety of loading conditions.
Inventors
- 👤 F Justice
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 19:32
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31924
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
238 words
A universal programmable interface line for intercoupling in accordance with stimulus or response information from an external memory, comprising terminal means for connecting the interface line to the external unit, line driver means for producing binary logic stimulus voltages at the terminal means, voltage comparator means for evaluating the magnitude of response signals applied to said terminal means by the external unit, programmable loading means for adjusting the impedance level at the terminal means, means for coupling said line driver means and said loading means to a programmable voltage source, means responsive to said stimulus or response information from said external memory for optionally enabling and disabling said line driver means and said voltage comparator means, and means for temporarily storing information derived from said voltage comparator means, said line driver means including a pair of output transistors arranged to be serially coupled across said programmable voltage source, said transistors being connected so that the emitter element of one transistor and the collector element of the other transistor are directly connected to said terminal means, said line driver means further including means responsive to said enabling means for saturating one or the other of said transistors when a stimulus signal of logic ONE or ZERO, respectively, is to be applied to said external unit. said loading means including resistor means and switching means for optionally coupling said terminal means to sources of known voltage through said resistor means.
Claim 2
Dependent Claim
238 words
A universal programmable interface line for intercoupling in accordance with stimulus or response information from an external memory, comprising terminal means for connecting the interface line to the external unit, line driver means for producing binary logic stimulus voltages at the terminal means, voltage comparator means for evaluating the magnitude of response signals applied to said terminal means by the external unit, programmable loading means for adjusting the impedance level at the terminal means, means for coupling said line driver means and said loading means to a programmable voltage source, means responsive to said stimulus or response information from said external memory for optionally enabling and disabling said line driver means and said voltage comparator means, and means for temporarily storing information derived from said voltage comparator means, said line driver means including a pair of output transistors arranged to be serially coupled across said programmable voltage source, said transistors being connected so that the emitter element of one transistor and the collector element of the other transistor are directly connected to said terminal means, said line driver means further including means responsive to said enabling means for saturating one or the other of said transistors when a stimulus signal of logic ONE or ZERO, respectively, is to be applied to said external unit. said loading means including resistor means and switching means for optionally coupling said terminal means to sources of known voltage through said resistor means.
Claim 3
Dependent Claim
35 words
The interface line of claim 1 wherein the switching means in said loading means includes first and second switches for optionally connecting said loading means to said programmable voltage source and to ground potential respectively.
Claim 4
Dependent Claim
27 words
The interface line of claim 2 wherein the resistor means includes first and second resistors coupled between said terminal means and said first and second switches respectively.
Claim 5
Dependent Claim
34 words
The interface line of claim 3 wherein said first and second resistors are selected so that said terminal means assumes a quiescent level intermittant logic ZERO and ONE levels when both switches are closed.
Claim 6
Dependent Claim
163 words
The interface line of claim 4 wherein the voltage comparator means includes first and second voltage comparators each having positive and negative input means and output means, said first comparator being arranged to receive at its positive input means a reference signal having a magnitude equal to the minimum acceptable mangitude of an expected logic ONE response signal, said second voltage comparator being arranged to receive at its negative input means, a reference signal having a magnitude equal to the maximum acceptable magnitude of an expected logic ZERO response signal, the remaining input means on both of said voltage comparators being connected directly to the terminal means of said interface line, said first and second voltage comparators further having their output means connected together, said voltage comparator means further containing means to enable only said first voltage comparator when a logic ONE response signal is expected and means to enable only said second voltage comparator when a logic ZERO response signal is expected.
Claim 7
Dependent Claim
42 words
The interface line of claim 5 wherein said means for temporarily storing information derived from said voltage comparator means includes a gated preset shift register arranged to accept information from either of said voltage comparators during the occurrence of a GATE pulse.
Claim 8
Dependent Claim
67 words
The interface line of claim 6 wherein the means for enabling and disabling the voltage comparator means includes a NOR gate connected to receive logic ONE enabling signals and logic ZERO disabling signals in response to instructions from an external memory, said NOR gate further being coupled to receive output signals from said voltage comparator means and to apply output signals to said gated preset shift register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-11-18 | 1978-05-20 | 1978-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-18 | 1982-05-20 | 1982-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-18 | 1986-05-20 | 1986-11-19 | $7700.00 | Window Closed / Lapsed |