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US3599098A Expired / Lapsed US ⏱️ 0.0 years remaining

Electronic testing apparatus

Assignee: American Microsystems Holding Corp
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Filing: 1969-02-25
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Granted: 1971-08-10
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Expires: 1989-02-25
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Abstract

Abstract A testing apparatus for logic circuit devices comprising a buffer amplifier pulse driver for driving capacitive loads with fast rise and fall times and for producing programmable output pulses at predetermined levels and in accordance with a predetermined logic pattern. The apparatus comprises a pair of operational amplifiers each adaptable to receive an input at a level equal to the desired output pulse. Each of the amplifiers has an output driver stage with an input connected to and driven by a current switch adaptable to receive a controlling logic input pulse in the same pattern desired at the apparatus output which is connected to the device being tested. The current switch provides the necessary drive to enable the output driver stages to bring the output to the desired level, and once that level is reached during each transition it is held constant by the operational amplifier until the next transition pulse from the logic input. The driver switches function to provide the pulse transitions to and from predetermined levels independent of the operational amplifiers and to hold the output at the desired level in conjunction with their operational amplifier.

Inventors

  • 👤 James H Mcphail

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-22 19:34
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31924

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 167 words
A buffer-amplifier pulse driver apparatus for providing an output variable to predetermined levels with fast rise and fall times comprising: a first level setting means adapted to receive a constant voltage input at a predetermined constant level; a second level setting means adapted to receive a constant voltage input at a predetermined constant level that is higher than the level to the first level setting means; a current switch adapted to receive an input with a predetermined timing pattern that is desired for the output of the apparatus and connected to outputs from both said level setting means; and a separate output driver means for each level setting means, each said driver means having an input connected to said current switch, said driver means being thereby actuated alternately to provide the output of the apparatus in a pulse pattern having precisely the same timing pattern received by said current switch with the pulses of the output pattern having the two levels supplied to said level setting means.
Claim 2
Dependent Claim 167 words
A buffer-amplifier pulse driver apparatus for providing an output variable to predetermined levels with fast rise and fall times comprising: a first level setting means adapted to receive a constant voltage input at a predetermined constant level; a second level setting means adapted to receive a constant voltage input at a predetermined constant level that is higher than the level to the first level setting means; a current switch adapted to receive an input with a predetermined timing pattern that is desired for the output of the apparatus and connected to outputs from both said level setting means; and a separate output driver means for each level setting means, each said driver means having an input connected to said current switch, said driver means being thereby actuated alternately to provide the output of the apparatus in a pulse pattern having precisely the same timing pattern received by said current switch with the pulses of the output pattern having the two levels supplied to said level setting means.
Claim 3
Dependent Claim 17 words
The apparatus as described in claim 1 wherein both said level setting means is an operational amplifier.
Claim 4
Dependent Claim 31 words
The apparatus as described in claim 1 wherein said output driver means comprises an NPN transistor and a PNP transistor connected to a common junction at the output of the apparatus.
Claim 5
Dependent Claim 90 words
The apparatus as described in claim 2 wherein each said operational amplifier comprises first and second transistors having emitters connected in parallel to a bias network from a voltage supply, said first transistor having a base connection to said junction and said second transistor having a base connection to the constant voltage level input of the operational amplifier, and a third transistor having its base connected to said second transistor and also to said current switch for maintaining the same level at said junction as applied to the operational amplifier.
Claim 6
Dependent Claim 108 words
The apparatus as described in claim 2 wherein said current switch comprises first and second transistors having emitters connected to a plus voltage supply, said first transistor having its base connected to the input to said current switch and its collector connected to said output driver means, third and fourth transistors connected to a negative voltage source with said third transistor connected to said output driver means, and means in said operational amplifiers for absorbing some of the current from either said first transistor or said third transistor to hold said driver means and thus the output of the apparatus at the levels applied to said operational amplifiers.
Claim 7
Dependent Claim 336 words
Apparatus for providing an output that will vary between predetermined levels with fast rise and fall times in accordance with a preset logic timing pattern that is desired for testing or exercising a logic circuit device, said apparatus comprising: a first operational ampliFier adapted to receive a constant voltage input at a predetermined constant level and having an output driver stage; a second operational amplifier adapted to receive a constant voltage at a predetermined level that is higher than the level supplied to said first operational amplifier, and having its own output driver stage; each said output driver stage having an output providing a feedback to the input of its operational amplifier and also an output for application to the semiconductor device under test; a logic generator means for providing pulses timed in predetermined logic pattern; a current switch having an input connected to said logic generator means for producing an output with the same said predetermined logic pattern, said current switch output being connected to the input of each said driver stage for both said operational amplifiers; and means connecting the output of each said operational amplifier to an interconnection between said current switch and the output driver stage of the other operational amplifier; whereby with the apparatus producing an output at the level of said first operational amplifier an output from said current switch in response to a transition signal from said logic generator causes both said operational amplifiers to become temporarily inoperative and the output driver stage for said second operational amplifier immediately commences a transition to its preset level, said second operational amplifier being responsive to its own output driver stage to become operative again and to maintain its preset output as its driver stage reaches this preset level, the process being reversed when said current switch receives another signal from said logic generator, the apparatus thereby producing a precise output alternately at the two preset levels of said operational amplifiers in accordance with the logic pattern supplied to said current switch.
Claim 8
Dependent Claim 336 words
Apparatus for providing an output that will vary between predetermined levels with fast rise and fall times in accordance with a preset logic timing pattern that is desired for testing or exercising a logic circuit device, said apparatus comprising: a first operational ampliFier adapted to receive a constant voltage input at a predetermined constant level and having an output driver stage; a second operational amplifier adapted to receive a constant voltage at a predetermined level that is higher than the level supplied to said first operational amplifier, and having its own output driver stage; each said output driver stage having an output providing a feedback to the input of its operational amplifier and also an output for application to the semiconductor device under test; a logic generator means for providing pulses timed in predetermined logic pattern; a current switch having an input connected to said logic generator means for producing an output with the same said predetermined logic pattern, said current switch output being connected to the input of each said driver stage for both said operational amplifiers; and means connecting the output of each said operational amplifier to an interconnection between said current switch and the output driver stage of the other operational amplifier; whereby with the apparatus producing an output at the level of said first operational amplifier an output from said current switch in response to a transition signal from said logic generator causes both said operational amplifiers to become temporarily inoperative and the output driver stage for said second operational amplifier immediately commences a transition to its preset level, said second operational amplifier being responsive to its own output driver stage to become operative again and to maintain its preset output as its driver stage reaches this preset level, the process being reversed when said current switch receives another signal from said logic generator, the apparatus thereby producing a precise output alternately at the two preset levels of said operational amplifiers in accordance with the logic pattern supplied to said current switch.
Claim 9
Dependent Claim 38 words
The apparatus as described in claim 6 wherein said logic generator means supplies a positive voltage input so that the output of the apparatus supplies a negative voltage output with the same logic pattern as the voltage input.

References Cited (Backward Citations)

US3274501A Cited
US3482116A Cited
US3453554A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-08-09 1975-02-08 1975-08-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-08-09 1979-02-08 1979-08-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-08-09 1983-02-08 1983-08-10 $7700.00 Window Closed / Lapsed

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