US3602809A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed function tester for integrated circuits
Assignee: National Institute of Advanced Industrial Science and Technology
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Filing: 1969-06-09
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Granted: 1971-08-31
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Expires: 1989-06-09
Abstract
Abstract The test apparatus is composed of a clock signal generating circuit, a patterned pulse generating circuit operated in synchronism with the clock signal generating circuit, with the output of the patterned pulse generating circuit being furnished to an integrated circuit to be tested, a reference voltage generating circuit, a comparator circuit to compare the output pulses from the integrated circuit to be tested with the output from the reference voltage generating circuit, a function pulse generating circuit synchronized with an output from the comparator circuit, a circuit for detecting coincidence between the output from the comparator circuit and the output from the function pulse generating circuit, and a displaying circuit to display the output of the coincidence detecting circuit, whereby the validity of the integrated circuit is determined from the coincidence of the output pulses from the integrated circuit with the expected pulse patterns obtained from the function pulse generating circuit.
Inventors
- 👤 Yasuo Tarui
- 👤 Yutaka Hayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 19:31
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
157 words
A functional test apparatus for integrated circuits comprising a clock signal generating circuit, a patterned pulse generating circuit operated in synchronism with the clock signal generating circuit so that the outputs of the patterned pulse generating circuit are furnished to an integrated circuit to be tested, a reference voltage generating circuit, a comparator circuit to compare the output pulses from the integrated circuit to be tested with the output from the reference voltage generating circuit, a function pulse generating circuit synchronized to an output from the comparator circuit, a circuit for detecting coincidence between the output from said comparator circuit and the output from the function pulse generating circuit, and a displaying circuit to display said output from the coincidence detecting circuit, whereby the validity in the function of the integrated circuit is determined from the coincidence of the output pulses from the integrated circuit with the expected pulse patterns obtained from the function pulse generating circuit.
Claim 2
Dependent Claim
157 words
A functional test apparatus for integrated circuits comprising a clock signal generating circuit, a patterned pulse generating circuit operated in synchronism with the clock signal generating circuit so that the outputs of the patterned pulse generating circuit are furnished to an integrated circuit to be tested, a reference voltage generating circuit, a comparator circuit to compare the output pulses from the integrated circuit to be tested with the output from the reference voltage generating circuit, a function pulse generating circuit synchronized to an output from the comparator circuit, a circuit for detecting coincidence between the output from said comparator circuit and the output from the function pulse generating circuit, and a displaying circuit to display said output from the coincidence detecting circuit, whereby the validity in the function of the integrated circuit is determined from the coincidence of the output pulses from the integrated circuit with the expected pulse patterns obtained from the function pulse generating circuit.
Claim 3
Dependent Claim
27 words
A test apparatus as defined in claim 1 wherein a control pulse generating circuit is further provided in the preceding stage of the clock signal generating circuit.
Claim 4
Dependent Claim
59 words
A test apparatus as defined in claim 1 wherein said patterned pulse generating circuit, output pulses of which are applied to said integrated circuit to be tested, is further provided with pulse pattern adjusting means whereby the rising time and decaying time of the pulses as well as their lower levels and higher levels can be adjusted as desired.
Claim 5
Dependent Claim
58 words
A test apparatus as defined in claim 1 wherein said comparator circuit is so arranged that another output complementary to said first output is delivered from said comparator circuit, said other output being thereafter supplied to another coincidence detecting circuit identical to said first coincidence detecting circuit, whereby erroneous operation of the test apparatus can be detected automatically.
Claim 6
Dependent Claim
18 words
A test apparatus as defined in claim 1 wherein said coincidence detecting circuit includes an ''''exclusive OR'''' circuit.
Claim 7
Dependent Claim
49 words
A test apparatus as defined in claim 1 wherein said synchronization of the function pulse generating circuit to an output of the comparator circuit is carried out through provision of a clock pulse generating circuit, said output from the comparator circuit being applied to said clock pulse generating circuit.
Claim 8
Dependent Claim
39 words
A test apparatus as defined in claim 1 wherein said synchronization of the function pulse generating circuit to an output of the comparator circuit is carried out through the employment of an output from said clock signal generating circuit.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-30 | 1975-03-01 | 1975-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-30 | 1979-03-01 | 1979-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-30 | 1983-03-01 | 1983-08-31 | $7700.00 | Window Closed / Lapsed |