US3728693A
Expired / Lapsed
US
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Programmatically controlled interrupt system for controlling input/output operations in a digital computer
Assignee: Unisys Corp
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Filing: 1972-04-28
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Granted: 1973-04-17
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Expires: 1992-04-28
Abstract
Abstract A digital computer system in which each input/output operation for transferring data between main memory and any one of a plurality of peripheral devices is initiated by a processor executing a Dispatch operation through an exchange associated with the main memory. In response to a Dispatch operation a designated input/output control unit examines a Result Status field of an associated input/output descriptor stored in main memory. The Result Status field defined by the descriptor indicates the current status of the input/output operation, namely, whether it has been completed or not. If not completed, the control unit performs the operation defined by the descriptor. When the input/output operation defined by the descriptor is completed, the Result Status field of the descriptor is again read out of main memory to the control unit and a new Result Status field written into the same location in memory, the new Result Status field indicating the operation has been completed and indicating whether or not there has been an exception condition, errors, etc. The control unit examines the prior Result Status field received from memory to determine if an interrupt of the processor is indicated. Only if an interrupt condition has been set in the prior Result Status field by the processor, the control unit initiates a Dispatch operation to the processor, signaling the processor that the operation is completed. If the interrupt condition is not set or if the interrupt condition has been set after the Dispatch operation is initiated, the control unit reads out a link address from the descriptor, and using the link address, reads out the Result Status field of another descriptor from memory. If the Result Status field of a descriptor, when first examined, indicates that the input/output descriptor has already been completed, the control unit continues to inspect the Result Status field at timed intervals until the Operation Complete condition is reset, in which case the input/output descriptor operation is again executed by the control unit.
Inventors
- 👤 J Macker
- 👤 W Keenan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 19:45
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
147 words
Control apparatus for transferring binary coded information between an input/output unit and an addressable memory in response to input/output descriptors stored in the memory, each input/output descriptor specifying an input/output operation and the address of a buffer area in memory, the control apparatus comprising accessing means responsive to an initiating signal for fetching at least a portion of a first input/output descriptor from memory, means including time delay means responsive to a first bit condition of said descriptor portion as fetched from memory by said accessing means for activating said accessing means to again fetch said same portion of said first descriptor from the memory after a predetermined time delay interval, and means responsive to a second bit condition of said descriptor portion when fetched from memory initiating transfer of information between the input/output unit and the buffer area in memory identified by said first input/output descriptor.
Claim 2
Dependent Claim
147 words
Control apparatus for transferring binary coded information between an input/output unit and an addressable memory in response to input/output descriptors stored in the memory, each input/output descriptor specifying an input/output operation and the address of a buffer area in memory, the control apparatus comprising accessing means responsive to an initiating signal for fetching at least a portion of a first input/output descriptor from memory, means including time delay means responsive to a first bit condition of said descriptor portion as fetched from memory by said accessing means for activating said accessing means to again fetch said same portion of said first descriptor from the memory after a predetermined time delay interval, and means responsive to a second bit condition of said descriptor portion when fetched from memory initiating transfer of information between the input/output unit and the buffer area in memory identified by said first input/output descriptor.
Claim 3
Dependent Claim
89 words
Apparatus as defined in claim 1 further comprising means indicating when the initiated transfer of information is completed, means setting said portion of the first input/output descriptor in memory to said first bit condition, means in response to an indication by said means indicating when the transfer operation is complete, and means fetching at least a portion of a second input/output descriptor from an address location in memory specified by the first input/output descriptor in response to an indication by said means indicating when the transfer operation is complete.
Claim 4
Dependent Claim
39 words
Apparatus as defined in claim 2 further including means storing the address of said descriptor portion in a predetermined location in memory in response to a predetermined bit condition when present in said descriptor portion of the first descriptor.
Claim 5
Dependent Claim
217 words
In a digital computer system having a processor, a main memory, a plurality of input/output devices, and control means for controlling transfer of data between memory and the processor and between memory and the input/output devices, a method of transferring data between an input/output device and memory comprising the steps of: storing a plurality of input/output descriptors in memory, each descriptor having coded bits indicating a particular operation, the address of a buffer area in memory, a group of status and control bits including an operation complete bit and interrupt request bit, on command from the processor initiating an input/output operation by fetching at least a portion of a first descriptor containing the operation complete bit from a location in memory identified by the processor, testing the operation complete bit, in response to a first condition of the operation complete bit, repeatedly fetching from memory and testing the operation complete bit in said first descriptor portion at predetermined time intervals, in response to a second condition of the operation complete bit when fetched from memory, executing the operation specified by the descriptor for transferring data between an input/output device and the specified buffer area in memory, and on completion of the data transfer, setting the operation complete bit in the descriptor in memory to said first condition.
Claim 6
Dependent Claim
217 words
In a digital computer system having a processor, a main memory, a plurality of input/output devices, and control means for controlling transfer of data between memory and the processor and between memory and the input/output devices, a method of transferring data between an input/output device and memory comprising the steps of: storing a plurality of input/output descriptors in memory, each descriptor having coded bits indicating a particular operation, the address of a buffer area in memory, a group of status and control bits including an operation complete bit and interrupt request bit, on command from the processor initiating an input/output operation by fetching at least a portion of a first descriptor containing the operation complete bit from a location in memory identified by the processor, testing the operation complete bit, in response to a first condition of the operation complete bit, repeatedly fetching from memory and testing the operation complete bit in said first descriptor portion at predetermined time intervals, in response to a second condition of the operation complete bit when fetched from memory, executing the operation specified by the descriptor for transferring data between an input/output device and the specified buffer area in memory, and on completion of the data transfer, setting the operation complete bit in the descriptor in memory to said first condition.
Claim 7
Dependent Claim
38 words
The method of claim 4 further comprising the steps of: at completion of the transfer operation, storing as part of the first descriptor the address in memory of the last data transferred between memory and the input/output device.
Claim 8
Dependent Claim
65 words
The method of claim 4 further comprising the steps of: when the data transfer is completed, fetching from memory at least a portion of the first descriptor including the interrupt request bit, testing the interrupt request bit, in response to a first condition of the interrupt request bit, providing an indication to the processor that the operation specified by the first descriptor has been completed.
Claim 9
Dependent Claim
37 words
The method of claim 6 further comprising the steps of: when the data transfer is completed, initiating another input/output operation by fetching at least a portion of a second descriptor from memory without intervention of the processor.
Claim 10
Dependent Claim
34 words
The method of claim 7 wherein: the step of fetching at least a portion of a second descriptor includes fetching the second descriptor from an address identified by a portion of the first descriptor.
Claim 11
Dependent Claim
162 words
Apparatus for controlling transfer of daTa between an input/output device and memory, comprising: means storing a plurality of digitally coded input/output descriptors, each descriptor having a status field for storing a plurality of control bits, an operation field for storing the input/output operation to be performed, a buffer address field identifying a buffer area in memory, and a link address field identifying the location of another input/output descriptor, accessing means for fetching the status field of a first descriptor from the descriptor storing means, means responsive to a first coded condition of the status field fetched from memory by the first accessing means for fetching the same status field at periodic time intervals as long as the first coded condition is present, and means responsive to a second condition of the status field when it is fetched from memory for executing the transfer operation specified by the operation field using the buffer area specified by the address field of the first descriptor.
Claim 12
Dependent Claim
162 words
Apparatus for controlling transfer of daTa between an input/output device and memory, comprising: means storing a plurality of digitally coded input/output descriptors, each descriptor having a status field for storing a plurality of control bits, an operation field for storing the input/output operation to be performed, a buffer address field identifying a buffer area in memory, and a link address field identifying the location of another input/output descriptor, accessing means for fetching the status field of a first descriptor from the descriptor storing means, means responsive to a first coded condition of the status field fetched from memory by the first accessing means for fetching the same status field at periodic time intervals as long as the first coded condition is present, and means responsive to a second condition of the status field when it is fetched from memory for executing the transfer operation specified by the operation field using the buffer area specified by the address field of the first descriptor.
Claim 13
Dependent Claim
47 words
Apparatus defined in claim 9 further comprising: means indicating when the transfer operation is completed, and means responsive to said indicating means for setting the status field of the first descriptor to said first coded condition in the descriptor storing means when the transfer operation is completed.
Claim 14
Dependent Claim
63 words
Apparatus as defined in claim 10 further comprising: means responsive to said indicating means for activating said accessing means to fetch the link address field of the first descriptor from the descriptor storing means when the transfer operation is complete, and means responsive to the link address for fetching the status field of the next descriptor at said link address location in memory.
Claim 15
Dependent Claim
300 words
A digital computer system comprising a main memory, a plurality of input/output devices for storing digital data, a plurality of input/output control units for controlling the transfer of digital data between main memory and the input/output devices, at least one processor, a memory exchange for controlling access to memory by the processor and the input/output control units, each input/output control unit having associated therewith and stored in the main memory a plurality of input/output descriptors each having an operation code, a beginning address of a buffer area in main memory, a result status field, and a link address pointing to another input/output descriptor, means in the memory exchange responsive to a group of signals from the processor for initiating an input/output operation by a designated control unit, the control unit including means reading out the result status field of a descriptor from main memory in response to said initiating means and storing it in the input/output control unit, means responsive to the operation complete bit in the result status field read out of memory when the bit is off for reading out the operation code and the beginning address from the associated descriptor in main memory and storing them in the input/output control, means responsive to the operation code for initiating an input/output data transfer operation between the input/output device associated with the designated control unit and main memory through the exchange starting at the beginning address in main memory, means generating a termination signal when the data transfer operation is completed, means responsive to the termination signal for reading the link address from the associated descriptor in main memory and storing it in the control unit, and means in the control unit reading out the result status field of the descriptor at the link address location in main memory.
Claim 16
Dependent Claim
300 words
A digital computer system comprising a main memory, a plurality of input/output devices for storing digital data, a plurality of input/output control units for controlling the transfer of digital data between main memory and the input/output devices, at least one processor, a memory exchange for controlling access to memory by the processor and the input/output control units, each input/output control unit having associated therewith and stored in the main memory a plurality of input/output descriptors each having an operation code, a beginning address of a buffer area in main memory, a result status field, and a link address pointing to another input/output descriptor, means in the memory exchange responsive to a group of signals from the processor for initiating an input/output operation by a designated control unit, the control unit including means reading out the result status field of a descriptor from main memory in response to said initiating means and storing it in the input/output control unit, means responsive to the operation complete bit in the result status field read out of memory when the bit is off for reading out the operation code and the beginning address from the associated descriptor in main memory and storing them in the input/output control, means responsive to the operation code for initiating an input/output data transfer operation between the input/output device associated with the designated control unit and main memory through the exchange starting at the beginning address in main memory, means generating a termination signal when the data transfer operation is completed, means responsive to the termination signal for reading the link address from the associated descriptor in main memory and storing it in the control unit, and means in the control unit reading out the result status field of the descriptor at the link address location in main memory.
Claim 17
Dependent Claim
48 words
Apparatus of claim 12 further comprising means in the control unit responsive to the operation complete bit in the result status field read out of memory when the bit is on for repeatedly reading out the result status field at intervals until the operation complete bit is off.
Claim 18
Dependent Claim
67 words
Apparatus of claim 12 further comprising means in the control unit responsive to the operation complete bit in the result status field read out of memory when the bit is on for reading out the link address from the associated descriptor and storing it in the control unit, and means for reading out the result status field of the descriptor at the link address location in memory.
Claim 19
Dependent Claim
48 words
Apparatus of claim 12 further including means responsive to said termination signal for again reading out the result status field of the descriptor from memory, and means writing into the same descriptor location in memory a new result status field in which the operation complete bit is on.
Claim 20
Dependent Claim
42 words
Apparatus as defined in claim 15 wherein the result status field includes an interrupt request bit, means in the control unit responsive to the interrupt request bit when it is on for signalling the processor that the data transfer operation is completed.
Claim 21
Independent Claim
183 words
The method of controlling the transfer of data between one or more peripheral devices and the working memory of a digital computer system having a processor and at least one peripheral control unit sharing said memory, the method comprising the steps of: storing a plurality of descriptors in main memory, each descriptor specifying an operation for transferring data between memory and a peripheral device, a buffer area in main memory, an operation complete flag indicating if the operation is completed or not completed, and a link address to another descriptor; initiating the read-out of a first one of the descriptors by the processor from memory to a peripheral control unit; executing in the control unit the operation specified by the descriptor; on completion of the execution of the operation, reading out a second one of the descriptors from the link address location in memory specified by the first descriptor to the peripheral control unit without intervention of the processor; and repeating the steps of executing the operation of the descriptor and reading out the next descriptor from the link address location in memory.
Claim 22
Independent Claim
183 words
The method of controlling the transfer of data between one or more peripheral devices and the working memory of a digital computer system having a processor and at least one peripheral control unit sharing said memory, the method comprising the steps of: storing a plurality of descriptors in main memory, each descriptor specifying an operation for transferring data between memory and a peripheral device, a buffer area in main memory, an operation complete flag indicating if the operation is completed or not completed, and a link address to another descriptor; initiating the read-out of a first one of the descriptors by the processor from memory to a peripheral control unit; executing in the control unit the operation specified by the descriptor; on completion of the execution of the operation, reading out a second one of the descriptors from the link address location in memory specified by the first descriptor to the peripheral control unit without intervention of the processor; and repeating the steps of executing the operation of the descriptor and reading out the next descriptor from the link address location in memory.
Claim 23
Dependent Claim
35 words
The method of claim 17 further including the steps of: at the completion of the execution of each descriptor operation, setting the flag in the corresponding descriptor in memory to indicate the operation is completed.
Claim 24
Dependent Claim
69 words
The method of claim 18 further including the steps of: on reading out each descriptor from memory to the control unit, testing the operation complete flag in the descriptor when the flag indicates the operation is completed, temporarily suspending execution of the descriptor operation and periodically reading out and testing the flag; when the flag indicates the operation is not completed, proceeding with the execution of the specified operation.
Claim 25
Dependent Claim
52 words
The method of claim 18 further including the steps of: on reading out each descriptor from memory to the control unit, testing the operation complete flag in the descriptor; when the flag indicates the operation is completed, reading out the next descriptor from the link address location specified by the current descriptor.
Claim 26
Dependent Claim
86 words
The method of claim 17 further including the steps of: storing with each descriptor in memory an interrupt request flag indicating if an interrupt of the processor is requested after execution of the descriptor operation; at the completion of the execution of each operation specified by a descriptor, reading out and testing the interrupt request flag from the same descriptor in memory; if the interrupt request flag indicates an interrupt of the processor is requested, dispatching an interrupt signal from the control unit to the processor.
Claim 27
Dependent Claim
40 words
The method of claim 17 further including the steps of: at the completion of the execution of each descriptor operation, generating a result status indication of the operation performed; storing the result status indication with the corresponding descriptor in memory.
Claim 28
Dependent Claim
45 words
The method of claim 17 further including the steps of: at the completion of the execution of each descriptoR operation, storing the final address of the buffer area in memory, used in executing the operation specified by the descriptor, with the corresponding descriptor in memory.
References Cited (Backward Citations)
US3411143A
Cited
US3588831A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-16 | 1976-10-16 | 1977-04-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-16 | 1980-10-16 | 1981-04-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-16 | 1984-10-16 | 1985-04-17 | $7700.00 | Window Closed / Lapsed |