US3699530A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input/output system with dedicated channel buffering
Assignee: International Business Machines Corp
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Filing: 1970-12-30
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Granted: 1972-10-17
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Expires: 1990-12-30
Abstract
Abstract A storage control unit (SCU) for a data processing system which buffers data fetch and data store requests from input/output channels for access to low-speed high-capacity interleaved logical storage units. Multiple dedicated buffers are provided for each channel in the storage control unit (SCU) to insure that all channels have an individual receptacle to transfer data to which cannot be made unavailable due to transfers by other channels. Priority resolution of requests from channels controls the use of the in bus from the channel to the SCU independently of subsequent priority resolution for use of the main storage. Once a channel transfers its storage address and data into its assigned SCU buffer, that buffer, based on the storage address contained within it, enters storage priority for the particular logical storage unit desired. In this manner, the single queue of channel requests is rearranged into four independent request queues based on logical storage addresses.
Inventors
- 👤 Robert S Capowski
- 👤 Robert M Unterberger
- 👤 Larry R Horsman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 19:49
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/18; G06F13/10; G06F13/12; G06F13/122
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
107 words
An input/output control system for controlling access to an interleaved memory divided into logical memory areas, comprising: a plurality of channels, each assigned a rank in a priority ranking order; a plurality of buffers at least one buffer for each channel, including means for storing requests comprising data and addresses of memory locations at which said data are to be stored; priority determining means responsive to addresses stored in said buffers for granting requests to an available one of said logical memory in the priority order said request holds in the ranking order with respect to requests by other channels in said order for the same memory.
Claim 2
Dependent Claim
107 words
An input/output control system for controlling access to an interleaved memory divided into logical memory areas, comprising: a plurality of channels, each assigned a rank in a priority ranking order; a plurality of buffers at least one buffer for each channel, including means for storing requests comprising data and addresses of memory locations at which said data are to be stored; priority determining means responsive to addresses stored in said buffers for granting requests to an available one of said logical memory in the priority order said request holds in the ranking order with respect to requests by other channels in said order for the same memory.
Claim 3
Dependent Claim
34 words
The combination according to claim 1 including priority means for granting priority to one of said channels at a time to access a common bus for transmitting said data and addresses to said buffers.
Claim 4
Dependent Claim
55 words
The combination according to claim 1 wherein said buffers comprise a predetermined number of buffers specifically dedicated to each channel; and including sequence monitor means for controlling the sequence of loading said predetermined number of said buffers specifically dedicated to a channel such that said buffers are loaded as they become available to said channel.
Claim 5
Dependent Claim
54 words
The combination according to claim 3 above wherein said plurality of buffers includes input buffers and output buffers and said sequence monitor includes means for maintaining a sequence of unloading said output buffers to said channel which sequence is the same sequence that said input buffers are loaded with said requests from said channel.
Claim 6
Dependent Claim
138 words
An input/output control system for controlling access to a memory having a plurality of independently accessible memory modules, comprising: means for selecting the module to which a given access request is made; means for indicating if said selected module is busy to said access request; a plurality of data channels having the capability of requesting access to said memory, said channels arranged in a priority order; a plurality of buffers, a predetermined number of said buffers specifically dedicated to each channel; a common bus interconnecting said channels and said buffers; and means responsive to manifestations corresponding to requests from said channels stored in said buffers, said manifestations corresponding to requests to access the same non-busy memory module, for granting access according to channel priority as among only those channels having requests pending for the same non-busy memory module.
Claim 7
Dependent Claim
138 words
An input/output control system for controlling access to a memory having a plurality of independently accessible memory modules, comprising: means for selecting the module to which a given access request is made; means for indicating if said selected module is busy to said access request; a plurality of data channels having the capability of requesting access to said memory, said channels arranged in a priority order; a plurality of buffers, a predetermined number of said buffers specifically dedicated to each channel; a common bus interconnecting said channels and said buffers; and means responsive to manifestations corresponding to requests from said channels stored in said buffers, said manifestations corresponding to requests to access the same non-busy memory module, for granting access according to channel priority as among only those channels having requests pending for the same non-busy memory module.
Claim 8
Dependent Claim
32 words
The combination according to claim 5 including priority means for granting priority to one of said channels at a time to access a common bus for transmitting said manifestations to said buffers.
Claim 9
Dependent Claim
40 words
The combination according to claim 5 including sequence monitor means for controlling the sequence of loading said predetermined number of said buffers specifically dedicated to a channel such that said buffers are loaded as they become available to said channel.
Claim 10
Dependent Claim
57 words
The combination according to claim 7 above wherein said plurality of buffers includes input buffers and output buffers and said sequence monitor includes means for maintaining a sequence of unloading said output buffers to said channel which sequence is the same sequence that said input buffers are loaded with said manifestations corresponding to requests from said channel.
Claim 11
Dependent Claim
128 words
For use in a system in which a plurality of users contend for a plurality of utilization devices, a priority circuit for resolving a plurality of said requests to use said utilization devices, in parallel comprising: means for individually indicating the availability of said utilization devices; means for registering manifestations of requests from each of said contenders, each of said registering means including means for indicating the utilization Device desired; and means responsive to said means for indicating the utilization device desired and to said availability signal for granting access to said device when said device becomes available and for not granting said request if manifestation of a request from a contender having a higher priority and for the same utilization device is registered in said registering means.
Claim 12
Dependent Claim
128 words
For use in a system in which a plurality of users contend for a plurality of utilization devices, a priority circuit for resolving a plurality of said requests to use said utilization devices, in parallel comprising: means for individually indicating the availability of said utilization devices; means for registering manifestations of requests from each of said contenders, each of said registering means including means for indicating the utilization Device desired; and means responsive to said means for indicating the utilization device desired and to said availability signal for granting access to said device when said device becomes available and for not granting said request if manifestation of a request from a contender having a higher priority and for the same utilization device is registered in said registering means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-17 | 1976-04-17 | 1976-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-17 | 1980-04-17 | 1980-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-17 | 1984-04-17 | 1984-10-17 | $7700.00 | Window Closed / Lapsed |