US5898186A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Reduced terminal testing system
Assignee: Micron Technology Inc
•
Filing: 1996-09-13
•
Granted: 1999-04-27
•
Expires: 2016-09-13
Abstract
Abstract A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer. In a preferred embodiment, the conductive path simultaneously carries a VCC power signal and the alternating signal to the circuitry. However, the alternating signal may be carried on a conductive path different from the one carrying the VCC signal. A great deal of information may be conveyed through the alternating signal, making other signals unnecessary in controlling, testing, stressing, and repairing dice on the wafer. For example, clocking information may be conveyed through the alternating signal. The circuitry may be placed in different modes in response to different characteristics of the alternating signal. The alternating signal and a VCC power signal are received through a single contact on each die. A wafer mode controlling system includes a system controller to control application of the alternating signals and other signals to the dice on the wafer. The semiconductor wafer mode controlling system may also control a probe positioning controller including an array of probes that selectively brings the probes into contact with the probe pads, whereby the alternating signal having the certain characteristics is transmitted from the probe to the circuitry through the probe pad and conductive path and the circuitry of each of the dice is placed into the mode.
Inventors
- 👤 Warren M. Farnworth
- 👤 Leland R. Nevill
- 👤 Raymond J. Beffa
- 👤 Eugene H. Cloud
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 01:31
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2855; G01R31/286; G01R31/2868; G01R31/2832; G01R31/2836; G01R31/2839; G01R31/2841; G01R31/2856; G01R31/317; G01R31/31701; G01R31/3181; G01R31/3185; G01R31/318505; G01R31/318511; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/1201; G11C29/48; H; H10; H10P; H10P74/00; H10P74/27; H10P74/273; G01R31/282; G01R31/2831
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
61 words
A semiconductor wafer comprising: a substrate; a plurality of dice located on the substrate, the plurality of dice including circuitry for placing an individual die of the plurality of dice into a mode upon receipt of an alternating signal having a predetermined characteristic by the circuitry; and a conductive path connected to the circuitry providing the alternating signal to the circuitry.
Claim 2
Dependent Claim
61 words
A semiconductor wafer comprising: a substrate; a plurality of dice located on the substrate, the plurality of dice including circuitry for placing an individual die of the plurality of dice into a mode upon receipt of an alternating signal having a predetermined characteristic by the circuitry; and a conductive path connected to the circuitry providing the alternating signal to the circuitry.
Claim 3
Dependent Claim
19 words
The wafer of claim 1, wherein the conductive path substantially simultaneously carries a VCC power signal to the circuitry.
Claim 4
Dependent Claim
17 words
The wafer of claim 2, wherein the alternating signal is substantially superimposed on the VCC power signal.
Claim 5
Dependent Claim
33 words
The wafer of claim 1, wherein the predetermined characteristic is a first characteristic, and whereby the circuitry is placed in a different mode in response to the alternating signal having a second characteristic.
Claim 6
Dependent Claim
126 words
The wafer of claim 1, wherein the plurality of dice is a first plurality of dice, the circuitry is a first set of circuitry, the mode is a first mode, the conductive path is a first path, the alternating signal is a first alternating signal, and the predetermined characteristic is a first characteristic, and wherein the wafer further comprises: a second plurality of dice on the substrate, the second plurality of dice including a second set of circuitry placing the second plurality of dice into a second mode when the second set of circuitry receives a second alternating signal having a second predetermined characteristic; and a second conductive path providing the second alternating signal to the second set of circuitry of the second plurality of dice.
Claim 7
Dependent Claim
18 words
The wafer of claim 5, wherein a predetermined reference signal is applied to the first plurality of dice.
Claim 8
Dependent Claim
73 words
The wafer of claim 1, wherein the plurality of dice is a first plurality of dice, the mode is a first mode, the alternating signal is a first alternating signal, and the predetermined characteristic is a first predetermined characteristic, and wherein the wafer further comprises a second plurality of dice, such second plurality of dice not being placed into the first mode in response to an alternating signal have the first predetermined characteristic.
Claim 9
Dependent Claim
29 words
The wafer of claim 1, wherein the circuitry includes first and second sections, and the first section receives the alternating signal including placing the second section into the mode.
Claim 10
Dependent Claim
16 words
The wafer of claim 1, wherein the mode includes a stressing mode for stressing the dice.
Claim 11
Dependent Claim
12 words
The wafer of claim 1, wherein the mode includes a repair mode.
Claim 12
Dependent Claim
28 words
The wafer of claim 1, wherein the alternating signal and a VCC power signal are received through a single contact on each die of the plurality of dice.
Claim 13
Dependent Claim
19 words
The wafer of claim 1, wherein the alternating signal includes a clock signal, the circuitry determining clock information therefrom.
Claim 14
Dependent Claim
23 words
The wafer of claim 1, wherein the plurality of dice include additional circuitry producing a signal indicating the occurrence of a predetermined event.
Claim 15
Dependent Claim
19 words
The wafer of claim 12, further comprising: a fuse, the fuse being blown at the completion of the mode.
Claim 16
Dependent Claim
19 words
The wafer of claim 12, further comprising: an anti-fuse, the anti-fuse being blown at the completion of the mode.
Claim 17
Dependent Claim
21 words
The wafer of claim 12, further comprising: a flash device, the flash device being blown at the completion of the mode.
Claim 18
Dependent Claim
46 words
The wafer of claim 1, further comprising: a plurality of street areas formed between adjacent individual die of the plurality of dice, the conductive path being formed in predetermined street areas of the plurality of street areas between predetermined individual die of the plurality of dice.
Claim 19
Dependent Claim
53 words
The wafer of claim 1, further comprising: a plurality of buffers connected to the conductive path, a predetermined individual buffer of the plurality of buffers preventing a predetermined individual die of the plurality of dice from receiving the alternating signal until such predetermined individual buffer associated with said predetermined individual die is enabled.
Claim 20
Dependent Claim
52 words
An electronic device, comprising: processing circuitry and memory circuitry, at least one of the processing and memory circuitry including: a substrate; and a die located on the substrate, the die including circuitry for placing the die into a mode upon receipt of an alternating signal having a predetermined characteristic by the circuitry.
Claim 21
Dependent Claim
52 words
An electronic device, comprising: processing circuitry and memory circuitry, at least one of the processing and memory circuitry including: a substrate; and a die located on the substrate, the die including circuitry for placing the die into a mode upon receipt of an alternating signal having a predetermined characteristic by the circuitry.
Claim 22
Dependent Claim
23 words
The device of claim 19, wherein the die includes a conductive path that substantially simultaneously carries a VCC power signal to the circuitry.
Claim 23
Dependent Claim
33 words
The device of claim 19, wherein the predetermined characteristic is a first characteristic, and whereby the circuitry is placed in a different mode in response to the alternating signal having a second characteristic.
Claim 24
Dependent Claim
12 words
The device of claim 19, wherein the device is a computer system.
Claim 25
Dependent Claim
11 words
The device of claim 19, wherein the device is a printer.
Claim 26
Dependent Claim
67 words
A semiconductor wafer comprising: a substrate; a plurality of dice located on the substrate, the plurality of dice each responding to a particular identification code and each including circuitry for placing individual die of the plurality of dice into a mode upon receipt of an alternating signal having the particular identification code; and a conductive path connected to the circuitry providing the alternating signal to the circuitry.
Claim 27
Dependent Claim
67 words
A semiconductor wafer comprising: a substrate; a plurality of dice located on the substrate, the plurality of dice each responding to a particular identification code and each including circuitry for placing individual die of the plurality of dice into a mode upon receipt of an alternating signal having the particular identification code; and a conductive path connected to the circuitry providing the alternating signal to the circuitry.
Claim 28
Dependent Claim
92 words
A semiconductor wafer comprising: a substrate; a conductive path associated with the substrate for carrying an alternating signal and another signal at the same time; and a plurality of dice fabricated on the substrate, with at least one of the dice including: an external terminal coupled to the conductive path for receiving the alternating signal and the other signal at the same time; and internal circuitry coupled to the external terminal for outputting an internal die signal substantially responsive to the alternating signal and at most insubstantially responsive to the other signal.
Claim 29
Dependent Claim
92 words
A semiconductor wafer comprising: a substrate; a conductive path associated with the substrate for carrying an alternating signal and another signal at the same time; and a plurality of dice fabricated on the substrate, with at least one of the dice including: an external terminal coupled to the conductive path for receiving the alternating signal and the other signal at the same time; and internal circuitry coupled to the external terminal for outputting an internal die signal substantially responsive to the alternating signal and at most insubstantially responsive to the other signal.
Claim 30
Dependent Claim
21 words
The semiconductor wafer of claim 25, further comprising a probe pad positioned on the substrate and coupled to the conductive path.
Claim 31
Dependent Claim
52 words
The semiconductor wafer of claim 25 wherein the conductive path comprises a conductive trace for carrying an alternating signal selected from a group comprising a digital signal and an analog signal and for carrying another signal selected from a group comprising a digital signal, an analog signal, and a supply voltage signal.
Claim 32
Dependent Claim
37 words
The semiconductor wafer of claim 27 wherein the conductive trace comprises a conductive trace for carrying an alternating signal selected from a group comprising an amplitude-modulated signal, a frequency-modulated signal, a pulse-width-modulated signal, and a phase-shift-keying-modulated signal.
Claim 33
Dependent Claim
97 words
The semiconductor wafer of claim 25 wherein the conductive path comprises a conductive trace for carrying an alternating signal comprising one-half of a differential alternating signal, wherein the semiconductor wafer further comprises an additional conductive path associated with the substrate for carrying the other half of the differential alternating signal, wherein the internal circuitry comprises differential circuitry, wherein the at least one die further comprises an additional external terminal coupled to the additional conductive path and the internal circuitry for receiving the other half of the differential alternating signal and conducting said signal to the internal circuitry.
Claim 34
Dependent Claim
14 words
The semiconductor wafer of claim 25 wherein the external terminal comprises a bond pad.
Claim 35
Dependent Claim
27 words
The semiconductor wafer of claim 25 wherein the internal circuitry includes at least one of filtering circuitry, clock extraction circuitry, buffering circuitry, differential circuitry, and demodulation circuitry.
Claim 36
Dependent Claim
31 words
The semiconductor wafer of claim 25 wherein the internal circuitry comprises circuitry for outputting at least one of an internal data signal, an internal control signal, and an internal clock signal.
Claim 37
Dependent Claim
43 words
The semiconductor wafer of claim 25 wherein the at least one die further comprises additional internal circuitry coupled to the external terminal for outputting another internal die signal substantially responsive to the other signal and at most insubstantially responsive to the alternating signal.
Claim 38
Dependent Claim
23 words
The semiconductor wafer of claim 33 wherein the additional internal circuitry comprises at least one of voltage regulation circuitry and input buffer circuitry.
Claim 39
Dependent Claim
39 words
The semiconductor wafer of claim 25 wherein the internal circuitry comprises an input buffer, wherein the at least one die further comprises an additional external terminal coupled to the input buffer for conducting an externally generated reference signal thereto.
Claim 40
Dependent Claim
38 words
The semiconductor wafer of claim 25 wherein the internal circuitry comprises demodulation circuitry, wherein the at least one die further comprises an additional external terminal coupled to the demodulation circuitry for conducting a reference local oscillator signal thereto.
References Cited (Backward Citations)
US3963985A
Cited
US4434401A
Cited
US5198752A
Cited
US5034688A
Cited
US5034685A
Cited
US4899107A
Cited
US4968931A
Cited
US5010296A
Cited
US5123850A
Cited
US5198753A
Cited
US5325052A
Cited
US5339273A
Cited
US5436559A
Cited
US5266894A
Cited
US5302891A
Cited
US5342807A
Cited
US5410261A
Cited
US5457401A
Cited
US5210485A
Cited
US5457400A
Cited
US5483175A
Cited
US5286656A
Cited
US5548884A
Cited
US5504369A
Cited
US5446695A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-26 | 2002-10-26 | 2003-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-26 | 2006-10-26 | 2007-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-26 | 2010-10-26 | 2011-04-27 | $7700.00 | Window Closed / Lapsed |