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US5453995A
Expired / Lapsed
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Apparatus for generating test signals
Assignee: Advantest Singapore Pte Ltd
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Filing: 1994-09-15
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Granted: 1995-09-26
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Expires: 2014-09-15
Abstract
Abstract An apparatus for generating test signals, preferably for use in an integrated circuit tester, comprises a sequencer, a Vector Memory and a Waveform Memory. The Vector Memory is addressed by the sequencer and contains coded waveform information, which is, in turn, decoded into control information by the Waveform Memory. For this purpose, the data outputs of the Vector Memory control the address inputs of the Waveform Memory. The data outputs of the Waveform Memory control circuitry like a formatter or a comparator which link the waveform information with timing information from one or more edge generators. The formatters, comparators etc. are, in turn, in connection with a device under test. The present apparatus provides full flexibility in the generation of formats and waveforms and, in particular, timing and format changes "on the fly", i.e. without additional delay. Flexibility may be increased if the Waveform Memory is reprogammable.
Inventors
- 👤 Klaus-Peter Behrens
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 11:11
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31928; G01R31/2832; G01R31/2836; G01R31/2839; G01R31/2841; G01R31/31922; G01R31/31919; G01R31/31921
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
201 words
Apparatus for generating test signals, comprising: first circuit means for generating address signals; first memory means for storing test vector signal patterns that define a waveform code or an action code, said first memory means having at least one address input connected to at least one output of said first circuit means and responsive to an address signal from said first circuit means to provide a test vector signal pattern output corresponding to said address signal; second circuit means for providing a format signal to a device under test and receiving data signals from a device under test; at least one edge generator for generating at an output, signal transitions that are substantially equidistant, the output of said edge generator connected to an input of said second circuit means; and second memory means including stored formatter control signals, interconnected between said first memory means and said second circuit means, said second memory means responsive to said test vector signal pattern that is output from said first memory means, to output a corresponding stored formatter control signal, said second circuit means responsive to said corresponding stored formatter control signal when said second circuit means receives a signal transition from said edge generator.
Claim 2
Dependent Claim
201 words
Apparatus for generating test signals, comprising: first circuit means for generating address signals; first memory means for storing test vector signal patterns that define a waveform code or an action code, said first memory means having at least one address input connected to at least one output of said first circuit means and responsive to an address signal from said first circuit means to provide a test vector signal pattern output corresponding to said address signal; second circuit means for providing a format signal to a device under test and receiving data signals from a device under test; at least one edge generator for generating at an output, signal transitions that are substantially equidistant, the output of said edge generator connected to an input of said second circuit means; and second memory means including stored formatter control signals, interconnected between said first memory means and said second circuit means, said second memory means responsive to said test vector signal pattern that is output from said first memory means, to output a corresponding stored formatter control signal, said second circuit means responsive to said corresponding stored formatter control signal when said second circuit means receives a signal transition from said edge generator.
Claim 3
Dependent Claim
30 words
Apparatus according to claim 1, wherein said formatter control signal from said second memory means defines a waveform for said format signal to be generated by said second circuit means.
Claim 4
Dependent Claim
38 words
Apparatus according to claim 1, wherein said second circuit means comprises an output driver and a data formatter that is responsive to said signal transition from said edge generator to provide, via said output driver, said format signal.
Claim 5
Dependent Claim
51 words
Apparatus according to claim 1, wherein said second circuit means comprises an output driver and a tri-state formatter that is responsive to said corresponding formatter control signal to control said output driver to either transmit to said device under test said format signal or to manifest a high impedance output state.
Claim 6
Dependent Claim
47 words
Apparatus according to claim 1, wherein said second circuit means comprises an edge comparator that is responsive to an output from said second memory means to determine if a data signal received from said device under test is an expected signal at a specific point in time.
Claim 7
Dependent Claim
57 words
Apparatus according to claim 5, wherein said second circuit means further comprises a window formatter that is responsive to said output from said second memory means to provide a window signal to said edge comparator to enable said edge comparator, during a time of said window signal, to respond to a signal from a device under test.
Claim 8
Dependent Claim
15 words
Apparatus according to claim 1, wherein said second circuit means comprises at least one flip-flop.
Claim 9
Dependent Claim
15 words
Apparatus according to claim 1, wherein said first memory means comprises an algorithmic pattern generator.
Claim 10
Dependent Claim
22 words
Apparatus according to claim 1, wherein said second memory means is programmable to enable alteration of said corresponding stored formatter control signal.
Claim 11
Dependent Claim
17 words
Apparatus according to claim 1, wherein said at least one edge generator is a static edge generator.
Claim 12
Dependent Claim
22 words
Apparatus according to claim 1, wherein said second memory means is integrated in an integrated circuit, together with said second circuit means.
Claim 13
Dependent Claim
28 words
Apparatus according to claim 1, wherein said second memory means includes substantially less inputs for receiving test vector signal patterns than outputs for providing stored formatter control signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-25 | 1999-03-27 | 1999-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-25 | 2003-03-27 | 2003-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-25 | 2007-03-27 | 2007-09-26 | $7700.00 | Window Closed / Lapsed |