Patent US4970300A successfully refreshed from Google Patents.
US4816750A
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Automatic circuit tester control system
Assignee: Teradyne Inc
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Filing: 1987-01-16
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Granted: 1989-03-28
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Expires: 2007-01-16
Abstract
Abstract Apparatus for providing high speed control of digital test patterns and analog instruments in automatic circuit testing apparatus including a sequence controller including a random access memory ("RAM") for microcode and an address generator for selectively addressing instructions in said random access memory, a sequence address bus connected to the address generator of the sequence controller, digital test pattern RAM connected to the sequence address bus, and analog instruments including associated RAM loaded with microcode for the instruments and connected to the sequence address bus.
Inventors
- 👤 Robert H. Van der Kloot
- 👤 Ernest P. Walker
- 👤 David L. Sulman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 08:17
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31907; G01R31/3167; G01R31/31917; G01R31/31919; G01R31/31921; G01R31/3193; G01R31/31935
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
155 words
Apparatus for providing high speed control of digital test patterns and analog instruments in automatic circuit testing apparatus for providing digital and analog test signals to and sensing responses from a circuit under test comprising a sequence controller including a sequence random access memory (RAM) loaded with microcode and a sequence address generator means for generating sequence addresses and selectively addressing instructions in said sequence RAM at the clock rate of said circuit under test, a sequence address bus connected to the sequence address generator to distribute sequence addresses appearing on it, a digital test pattern RAM connected to be addressed by said sequence addresses on said sequence address bus, said digital test pattern RAM being loaded with digital test patterns to be applied to said circuit under test, and analog instruments including associated instrument RAMs loaded with microcode for the instruments and connected to be addressed by sequence addresses on said sequence address bus.
Claim 2
Dependent Claim
155 words
Apparatus for providing high speed control of digital test patterns and analog instruments in automatic circuit testing apparatus for providing digital and analog test signals to and sensing responses from a circuit under test comprising a sequence controller including a sequence random access memory (RAM) loaded with microcode and a sequence address generator means for generating sequence addresses and selectively addressing instructions in said sequence RAM at the clock rate of said circuit under test, a sequence address bus connected to the sequence address generator to distribute sequence addresses appearing on it, a digital test pattern RAM connected to be addressed by said sequence addresses on said sequence address bus, said digital test pattern RAM being loaded with digital test patterns to be applied to said circuit under test, and analog instruments including associated instrument RAMs loaded with microcode for the instruments and connected to be addressed by sequence addresses on said sequence address bus.
Claim 3
Dependent Claim
21 words
The apparatus of claim 1 wherein said analog instruments include an analog signal generator and a capture digitizer and associated memory.
Claim 4
Dependent Claim
23 words
The apparatus of claim 2 wherein said analog instruments comprise high frequency and low frequency signal generators and capture digitizers and associated memories.
Claim 5
Dependent Claim
31 words
The apparatus of claim 1 further comprising instruments that provide and detect digital representations of analog signals and have associated RAMs loaded with microcode and connected to said sequence address bus.
Claim 6
Dependent Claim
51 words
The apparatus of claim 2 wherein said analog signal generator comprises a signal microcode RAM connected to said sequence address bus, a signal address generator provided with instructions from said signal microcode, a signal RAM loaded with digitized analog signals and addressed by said signal address generator, and a D/A converter.
Claim 7
Dependent Claim
36 words
The apparatus of claim 1 wherein there is a clock RAM loaded with microcode for the clock and connected to said sequence address bus and a clock generator controlled by said microcode in said clock RAM.
Claim 8
Dependent Claim
28 words
The apparatus of claim 1 wherein said sequence address bus includes pipeline registers to sequentially advance address information along the address bus from the address generator upon clocking.
Claim 9
Dependent Claim
28 words
The apparatus of claim 1 wherein said sequence address bus includes a condition bit that can be used to affect the address generated by the sequence address generator.
References Cited (Backward Citations)
US4402055A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-27 | 1992-09-26 | 1993-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-27 | 1996-09-26 | 1997-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-27 | 2000-09-26 | 2001-03-28 | $7700.00 | Window Closed / Lapsed |