Patent US5353254A successfully refreshed from Google Patents.
US5353254A
Expired / Lapsed
US
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Semiconductor memory device having burn-in test circuit
Assignee: Texas Instruments Inc
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Filing: 1992-05-21
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Granted: 1994-10-04
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Expires: 2012-05-21
Abstract
Abstract The described embodiments of the disclosed invention provide a semiconductor devices, test apparatus for the semiconductor devices and a method for testing the semiconductor devices. The semiconductor devices may have many different types of pin counts and configurations. Each semiconductor device includes standardized test circuitry. The necessary pins to operate the test circuitry are included in a standardized position on the semiconductor devices relative to the positioning of the semiconductor devices in the test apparatus. Thus a single test apparatus may be utilized to test semiconductor devices having a wide range of pin configurations.
Inventors
- 👤 Harumi Sakamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:56
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/273; G06F11/2733; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/48
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
153 words
A system for testing a plurality of types of packaged integrated circuits having a plurality of pin configurations comprising: a socket capable of receiving said plurality of pin configurations; a reference voltage terminal provided at a first physical pin location of said socket, each of said integrated circuits having a pin for receiving said reference voltage at said first physical pin location; a supply voltage terminal provided at a second physical pin location of said socket, each of said integrated circuits having a pin for receiving said supply voltage at said second physical pin location; and at least one control signal terminal provided at a third physical pin location of said socket, each of said integrated circuits including a test circuit for receiving said control signal source and generating control signals appropriate for that integrated circuit, and each integrated circuit having a pin for receiving said control signal at said third physical location.
Claim 2
Independent Claim
153 words
A system for testing a plurality of types of packaged integrated circuits having a plurality of pin configurations comprising: a socket capable of receiving said plurality of pin configurations; a reference voltage terminal provided at a first physical pin location of said socket, each of said integrated circuits having a pin for receiving said reference voltage at said first physical pin location; a supply voltage terminal provided at a second physical pin location of said socket, each of said integrated circuits having a pin for receiving said supply voltage at said second physical pin location; and at least one control signal terminal provided at a third physical pin location of said socket, each of said integrated circuits including a test circuit for receiving said control signal source and generating control signals appropriate for that integrated circuit, and each integrated circuit having a pin for receiving said control signal at said third physical location.
Claim 3
Dependent Claim
34 words
The system of claim 1 wherein said supply voltage provided on said supply voltage terminal is greater than a normal supply level for periods of time determined to coordinate temporally with said control signal.
Claim 4
Dependent Claim
12 words
The system of claim 1 wherein said system performs a burn-in test.
Claim 5
Dependent Claim
12 words
The system of claim 1 wherein said integrated circuits are memory circuits.
Claim 6
Dependent Claim
13 words
The system of claim 1 wherein said integrated circuits are programmable gate arrays.
Claim 7
Dependent Claim
18 words
The system of claim 1 further comprising means of elevating the temperature of the integrated circuit being tested.
Claim 8
Dependent Claim
31 words
The system of claim 6 wherein said means of elevating the temperature of the integrated circuit is capable of raising the temperature of the integrated circuit to at least 125° C.
Claim 9
Dependent Claim
17 words
The system of claim 1 wherein said pin configurations include 70 and 36 pin dual in-line packages.
Claim 10
Dependent Claim
32 words
The system of claim 1 wherein said at least one control signal comprises a first, second and third control signals provided at said third, a fourth and a fifth pin position, respectively.
Claim 11
Independent Claim
162 words
A method of testing a plurality of types of packaged integrated circuits having a plurality of pin configurations in a single testing system, comprising the steps of: providing a socket capable of receiving said plurality of pin configurations; providing a reference voltage terminal at a first physical pin location of said socket, each of said integrated circuits having a pin for receiving said reference voltage at said first physical pin location; providing a supply voltage terminal at a second physical pin location of said socket, each of said integrated circuits having a pin for receiving said supply voltage at said second physical pin location; and providing at least one control signal terminal at a third physical pin location of said socket, each of said integrated circuits including a test circuit for receiving said control signal source and generating control signals appropriate for that integrated circuit, and each integrated circuit having a pin for receiving said control signal at said third physical location.
Claim 12
Independent Claim
162 words
A method of testing a plurality of types of packaged integrated circuits having a plurality of pin configurations in a single testing system, comprising the steps of: providing a socket capable of receiving said plurality of pin configurations; providing a reference voltage terminal at a first physical pin location of said socket, each of said integrated circuits having a pin for receiving said reference voltage at said first physical pin location; providing a supply voltage terminal at a second physical pin location of said socket, each of said integrated circuits having a pin for receiving said supply voltage at said second physical pin location; and providing at least one control signal terminal at a third physical pin location of said socket, each of said integrated circuits including a test circuit for receiving said control signal source and generating control signals appropriate for that integrated circuit, and each integrated circuit having a pin for receiving said control signal at said third physical location.
Claim 13
Dependent Claim
38 words
The method of claim 10 wherein said supply voltage provided on said supply voltage terminal is provided at a level greater than a normal supply level for periods of time determined to coordinate temporally with said control signal.
Claim 14
Dependent Claim
15 words
The method of claim 10 wherein said method is used to perform a burn-in test.
Claim 15
Dependent Claim
12 words
The method of claim 10 wherein said integrated circuits are memory circuits.
Claim 16
Dependent Claim
13 words
The method of claim 10 wherein said integrated circuits are programmable gate arrays.
Claim 17
Dependent Claim
19 words
The method of claim 10 further comprising the step of elevating the temperature of the integrated circuit being tested.
Claim 18
Dependent Claim
28 words
The system of claim 15 wherein said step of elevating the temperature of the integrated circuit raises the temperature of the integrated circuit to at least 125° C.
Claim 19
Dependent Claim
17 words
The system of claim 10 wherein said pin configurations include 70 and 36 pin dual in-line packages.
Claim 20
Dependent Claim
32 words
The system of claim 10 wherein said at least one control signal comprises a first, second and third control signals provided at said third, a fourth and a fifth pin position, respectively.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-03 | 1998-04-04 | 1998-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-03 | 2002-04-04 | 2002-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-03 | 2006-04-04 | 2006-10-04 | $7700.00 | Window Closed / Lapsed |