Semiconductor integrated circuit adapted to carry out operation test

Claim 1

A semiconductor integrated circuit device adapted to carry out a test operation, comprising: an internal memory circuit operating under one of a normal mode and test mode, including: a memory cell array; a row decoder circuit coupled to said memory cell array; a column gate circuit coupled to said memory cell array; and a column decoder circuit coupled to said column gate circuit; a plurality of input and output terminals connected to said internal memory circuit; a high voltage detector circuit, connected to one of said input and output terminals, for outputting a control signal only when a predetermined voltage higher than a power source voltage is applied to one of said input and output terminals; latch means, connected to said row and column decoders, to said internal memory circuit and to one of said input and output terminals not connected to said high voltage detector circuit, for latching an input signal in response to said control signal from said high voltage detector circuit; buffer means, connected to said latch means and said internal memory circuit, for receiving input and output signals; and selection means, coupled to said buffer means, for selecting one of the normal mode and test mode of said internal memory circuit in accordance with the input signal latched by said latch means.