Programmable wait states generator for a microprocessor and computer system utilizing it

Claim 1

A computer system, comprising: a data bus, a central processing unit (CPU) connected to said data bus and having a machine cycle of a pre-determined minimum number of clock cycles in duration for reading an operational code segment from a memory connected to said data bus, and for reading a return from interrupt (RETI) operational code on said data bus, said RETI operational code having first and second segments as part of a set of instructions stored in said memory, thereby requiring first and second successive machine cycles to read said return from interrupt operational code from the memory, a plurality of peripheral circuits connected to said data bus, connected by a common interrupt line to said CPU, and connected with each other via a daisy chain configuration such that the CPU can service one interrupt request from one peripheral circuit at a time, said peripheral circuits being individually responsive to said return from interrupt operational code, whereby the response to such a return from interrupt operational code functions to terminate an operation initiated after a peripheral circuit has generated an interrupt request to said CPU over said common interrupt line, and second machine cycle lengthening means in communication with said data bus and said CPU, said second machine cycle lengthening means including means for detecting on said data bus said first machine cycle of the first segment of said return from interrupt operational code, wherein said second machine cycle lengthening means is responsive to detection of said first machine cycle of the first segment of said return from interrupt operational code for causing said CPU to insert a programmable number of additional clock cycles into said second machine cycle, whereby additional time is provided for the daisy chain peripheral circuits to respond to the return from interrupt operational code before an end of said first and second machine cycles.