Variable latency method and apparatus for floating-point coprocessor

Claim 3

The apparatus of claim 1 further comprising: a second arithmetic logic means, including a multiplier, for performing multiply operations on said operands upon receipt of a provided multiplier start signal; second counter means for producing a multiply done signal a predetermined number of cycles of said clock after said multiplier start signal; and second programmable means, coupled to an input of said second counter means, for varying said number of cycles of said clock required to produce said multiply done signal, such that a latency between said multiplier start signal and said multiply done signals can be minimized for varying cycle times of said clock.

Claim 8

The apparatus of claim 4 wherein said counter means further comprises second logic means, coupled between said programmable means and said counter, for decoding an output of said programmable means and for preventing a zero value being presented to said counter.

Claim 9

The apparatus of claim 4 wherein said logic means includes means for inhibiting said completion signal while said start signal is received.

Claim 12

The apparatus of claim 7 wherein some of said input bonding pads are coupled to a voltage reference through a resistor on said chip.

Claim 13

The apparatus of claim 7 wherein some of said input bonding pads are coupled to a voltage reference via bonding wires connected to package bonding fingers.

Claim 14

The apparatus of claim 7 wherein some of said input bonding pads are coupled to an input pin.

Claim 15

A coprocessor for performing arithmetic operations on supplied operands and using a clock, comprising: first arithmetic logic means for performing an arithmetic operation on said operands upon receipt of a provided arithmetic start signal; first counter means for producing an arithmetic done signal a predetermined number of cycles of said clock after said arithmetic start signal; first programmable means, coupled to an input of said first counter means, for varying said number of cycles of said clock required to produce said arithmetic done signal, such that a latency between said arithmetic start and arithmetic done signals can be controlled; a second arithmetic logic means, including a multiplier, for performing multiply operations on said operands upon receipt of a provided multiplier start signal; second counter means for producing a multiply done signal a predetermined number of cycles of said clock after said multiplier start signal; second programmable means, coupled to an input of said second counter means, for varying said number of cycles of said clock required to produce said multiply done signal, such that a latency between said multiplier start signal and said multiply done signals can be controlled; third programmable means for selecting a variable number of cycles for divide iterations; and means, coupled to said third programmable means, for providing a divide clock to one of said arithmetic logic means.

Claim 16

A coprocessor for performing arithmetic operations on supplied operands and using a clock, comprising: first arithmetic logic means for performing an arithmetic operation on said operands upon receipt of a provided arithmetic start signal; first counter means for producing an arithmetic done signal a predetermined number of cycles of said clock after said arithmetic start signal; first programmable means, coupled to an input of said first counter means, for varying said number of cycles of said clock required to produce said arithmetic done signal, such that a latency between said arithmetic start and arithmetic done signals can be controlled; a second arithmetic logic means, including a multiplier, for performing multiply operations on said operands upon receipt of a provided multiplier start signal; second counter means for producing a multiply done signal a predetermined number of cycles of said clock after said multiplier start signal; second programmable means, coupled to an input of said second counter means, for varying said number of cycles of said clock required to produce said multiply done signal, such that a latency between said multiplier start signal and said multiply done signals can be controlled; third programmable means for selecting a variable number of cycles for divide iterations; and means, coupled to said third programmable means, for providing a divide clock to one of said arithmetic logic means.

Claim 17

A coprocessor for performing arithmetic operations on supplied operands and using a clock, comprising: first arithmetic logic means for performing an arithmetic operation on said operands upon receipt of a provided arithmetic start signal; first counting means for producing an arithmetic done signal a predetermined number of cycles of said clock after said arithmetic start signal, said first counting means including a first counter having an input for receiving a first starting count, first logic means, coupled to an output of said first counter, for producing a completion signal when said first counter output is equal to a first predetermined value, and a first register coupled to an output of said first logic means for producing said arithmetic done signal at its output upon a next clock cycle after said first logic means receives said first predetermined value; first programmable means, coupled to said input of said first counting means, for providing said first starting count to control said number of cycles of said clock required to produce said arithmetic done signal, such that a latency between said arithmetic start and arithmetic done signals can be controlled based on the cycle time of said clock; a second arithmetic logic means, including a multiplier, for performing multiply operations on said operands upon receipt of a provided multiplier start signal; second counting means for producing a multiply done signal a predetermined number of cycles of said clock after said multiplier start signal, said second counting means including a second counter having an input for receiving a second starting count, second logic means, coupled to an output of said second counter, for producing a second completion signal when said second counter output is equal to a second predetermined value, and a second register coupled to an output of said second logic means for producing said multiply done signal at its output upon a next clock cycle after said second logic means receives said second predetermined value; second programmable means, coupled to said input of said second counter, for providing said second starting count to control said number of cycles of said clock required to produce said multiply done signal, such that a latency between said multiplier start signal and said multiply done signals can be controlled; third programmable means for selecting a variable number of cycles for divide iterations; and means, coupled to said third programmable means, for providing a divide clock to one of said arithmetic logic means.

Claim 18

A coprocessor for performing arithmetic operations on supplied operands and using a clock, comprising: first arithmetic logic means for performing an arithmetic operation on said operands upon receipt of a provided arithmetic start signal; first counting means for producing an arithmetic done signal a predetermined number of cycles of said clock after said arithmetic start signal, said first counting means including a first counter having an input for receiving a first starting count, first logic means, coupled to an output of said first counter, for producing a completion signal when said first counter output is equal to a first predetermined value, and a first register coupled to an output of said first logic means for producing said arithmetic done signal at its output upon a next clock cycle after said first logic means receives said first predetermined value; first programmable means, coupled to said input of said first counting means, for providing said first starting count to control said number of cycles of said clock required to produce said arithmetic done signal, such that a latency between said arithmetic start and arithmetic done signals can be controlled based on the cycle time of said clock; a second arithmetic logic means, including a multiplier, for performing multiply operations on said operands upon receipt of a provided multiplier start signal; second counting means for producing a multiply done signal a predetermined number of cycles of said clock after said multiplier start signal, said second counting means including a second counter having an input for receiving a second starting count, second logic means, coupled to an output of said second counter, for producing a second completion signal when said second counter output is equal to a second predetermined value, and a second register coupled to an output of said second logic means for producing said multiply done signal at its output upon a next clock cycle after said second logic means receives said second predetermined value; second programmable means, coupled to said input of said second counter, for providing said second starting count to control said number of cycles of said clock required to produce said multiply done signal, such that a latency between said multiplier start signal and said multiply done signals can be controlled; third programmable means for selecting a variable number of cycles for divide iterations; and means, coupled to said third programmable means, for providing a divide clock to one of said arithmetic logic means.