Method for servicing a peripheral interrupt request in a microcontroller

Claim 2

In a data processing system having a processor for executing a sequence of instructions provided by a memory in response to a sequence of instruction addresses, and having a selected number of peripheral devices coupled to said processor via an internal communications bus a method for servicing an interrupt request from one of the selected number of peripheral devices, comprising the steps of: storing an index value in an addressable register in an interrupting peripheral device, in response to said interrupting peripheral device generating an interrupt request, said index value comprising at least a first bit field representing a current state identifier for identifying a state of a state machine which controls said interrupting peripheral device, and a second bit field representing an incremental byte boundary identifier, said incremental byte boundary identifier being determined by entry alignment in a table in said memory of each of a plurality of interrupt service routines; providing said index value to said processor, via said internal communications bus, said processor using said index value to access a corresponding interrupt service routine, stored in said table in said memory, for responding to said interrupt request; updating, during execution by said processor of said interrupt service routine, said current state identifier stored in said addressable register with a next state identifier, by modifying said first bit field of said index value, in response to said state machine changing states as result of an occurrence in said interrupting peripheral device of a predefined event, said next state identifier and said incremental byte boundary identifier forming a new index value in said addressable register; and executing said interrupt service routine to clear said interrupt service request.

Claim 3

The method for servicing an interrupt request according to claim 1 further comprising the step of providing said new index value to said processor, via said internal communications bus, said new index value being used by said processor to access a new interrupt service routine, in said table in said memory, for a new interrupt request.

Claim 4

In a data processing system comprising: a processor; an internal communications bus coupled to said processor; a memory coupled to said internal communications bus, said memory storing a plurality of table entries for a plurality of interrupt service routines; a predetermined number of peripheral devices coupled to said processor, via said internal communications bus, a selected peripheral device having a plurality of addressable registers for storing control information, for providing status information, and for allowing the exchange of a plurality of data bytes to and from said processor; a method for servicing an interrupt request received by said processor for an interrupting peripheral, comprising the steps of: storing a current state identifier, for a state machine which controls said interrupting peripheral device, in a first bit field in a first addressable register in said interrupting peripheral device; storing an interrupt priority identifier in a second bit field in said first addressable register, said interrupt priority identifier signifying a source in said interrupting peripheral device of said interrupt service request, according to an interrupt priority scheme; storing a value in a third bit field of said first addressable register, said value being based upon an incremental byte boundary determined by alignment in said memory of each of said plurality of table entries for said plurality of interrupt service routines; updating, during execution by said processor of said interrupt service routine, said current state identifier stored in said first addressable register with a next state identifier, in response to said state machine changing states, said next state identifier, said interrupt priority field, and said third bit field forming an index offset value in said first addressable register; and providing said index offset value to said processor, said index offset value being used by said processor as an index into said plurality of table entries in said memory, said processor executing a corresponding one of said plurality of interrupt service routines to clear said interrupt service routine.

Claim 5

In a data processing system comprising: a processor; an internal communications bus coupled to said processor; a memory coupled to said internal communications bus, said memory storing a plurality of table entries for a plurality of interrupt service routines; a predetermined number of peripheral devices coupled to said processor, via said internal communications bus, a selected peripheral device having a plurality of addressable registers for storing control information, for providing status information, and for allowing the exchange of a plurality of data bytes to and from said processor; a method for servicing an interrupt request received by said processor for an interrupting peripheral, comprising the steps of: storing a current state identifier, for a state machine which controls said interrupting peripheral device, in a first bit field in a first addressable register in said interrupting peripheral device; storing an interrupt priority identifier in a second bit field in said first addressable register, said interrupt priority identifier signifying a source in said interrupting peripheral device of said interrupt service request, according to an interrupt priority scheme; storing a value in a third bit field of said first addressable register, said value being based upon an incremental byte boundary determined by alignment in said memory of each of said plurality of table entries for said plurality of interrupt service routines; updating, during execution by said processor of said interrupt service routine, said current state identifier stored in said first addressable register with a next state identifier, in response to said state machine changing states, said next state identifier, said interrupt priority field, and said third bit field forming an index offset value in said first addressable register; and providing said index offset value to said processor, said index offset value being used by said processor as an index into said plurality of table entries in said memory, said processor executing a corresponding one of said plurality of interrupt service routines to clear said interrupt service routine.

Claim 6

The method of servicing an interrupt request according to claim 3 further comprising the step of simultaneously updating said second bit field with a next priority interrupt identifier to form a new index offset value in said first addressable register, said new offset value being provided to said processor, and said processor using said new index offset value as a new index into said plurality of table entries in said memory.

Claim 7

The method for servicing an interrupt request according to claim 4 wherein said step of simultaneously updating said second bit field with said next priority interrupt identifier is repeated in said data processing system until a value stored in said second bit field indicates that no further interrupt request are pending.

Claim 8

In a data processing system having a processor for executing a sequence of instructions provided by a memory in response to a corresponding sequence of instruction addresses, and having a selected number of peripheral devices coupled to said processor, via an internal communications bus, a method for servicing an interrupt request from an interrupting peripheral device comprising the steps of: storing a current state identifier in a first bit field in a software addressable register in said interrupting peripheral device, said current state identifier signifying a current state of said interrupting peripheral device; storing an interrupt priority identifier in a second bit field in said software addressable register, said interrupt priority identifier signifying a source in said interrupting peripheral device of said interrupt service request, according to a predetermined interrupt priority scheme; updating, during execution by said processor of said interrupt service routine, said current state identifier stored in said software addressable register with a next state identifier, in response to said interrupting peripheral changing states, said next state identifier and said interrupt priority identifier forming an index offset value in said software addressable register; providing said index offset value to said processor, via said internal communications bus, said index offset value being used, by said processor as an index into a jump table in said memory, to retrieve a corresponding interrupt service routine; and executing said interrupt service routine to clear said interrupt service request.

Claim 9

In a data processing system having a processor for executing a sequence of instructions provided by a memory in response to a corresponding sequence of instruction addresses, and having a selected number of peripheral devices coupled to said processor, via an internal communications bus, a method for servicing an interrupt request from an interrupting peripheral device comprising the steps of: storing a current state identifier in a first bit field in a software addressable register in said interrupting peripheral device, said current state identifier signifying a current state of said interrupting peripheral device; storing an interrupt priority identifier in a second bit field in said software addressable register, said interrupt priority identifier signifying a source in said interrupting peripheral device of said interrupt service request, according to a predetermined interrupt priority scheme; updating, during execution by said processor of said interrupt service routine, said current state identifier stored in said software addressable register with a next state identifier, in response to said interrupting peripheral changing states, said next state identifier and said interrupt priority identifier forming an index offset value in said software addressable register; providing said index offset value to said processor, via said internal communications bus, said index offset value being used, by said processor as an index into a jump table in said memory, to retrieve a corresponding interrupt service routine; and executing said interrupt service routine to clear said interrupt service request.

Claim 10

The method of servicing an interrupt request according to claim 6 further comprising the step of updating said second bit field with a lower priority interrupt identifier to provide a new index offset value to said processor, said new index offset value being used by said processor to retrieve a new interrupt service routine from said memory.

Claim 11

The method of servicing an interrupt request according to claim 7 wherein said step of updating said second bit field with said lower priority interrupt identifier is repeated in said data processing system until a value, stored in said second bit field, indicates that no further interrupt requests are pending.