US4037204A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprocessor interrupt logic
Assignee: Motorola Solutions Inc
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Filing: 1975-09-17
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Granted: 1977-07-19
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Expires: 1995-09-17
Abstract
Abstract Interrupt circuitry is provided for an MOS integrated circuit microprocessor chip. An input of the microprocessor chip is adapted to having an external interrupt signal applied thereto for interrupting the operation of the microprocessor chip within a digital data processing system. The input is coupled to circuitry which inhibits loading of the next instruction to be executed in response to an interrupt request signal applied to the interrupt request input, and also forces a code into the instruction register in response to the interrupt request signal. The code is substantially similar to the code for a software wait instruction or a software interrupt instruction. Therefore, much of the same circuitry within the microprocessor can be used for executing an interrupt operation, a software wait instruction, or a software interrupt instruction.
Inventors
- 👤 Thomas H. Bennett
- 👤 Earl F. Carlow
- 👤 Anthony E. Kouvoussis
- 👤 Rodney H. Orgill
- 👤 Charles Peddle
- 👤 Michael F. Wiles
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 10:02
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F9/30; G06F9/30003; G06F9/30076; G06F9/30079; G06F9/32; G06F9/34; G06F9/342; G06F9/355; G06F9/3557
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
191 words
A microprocessor comprising: a data bus means for transferring digital information; an interrupt request input conductor for conducting an interrupt request input signal representative of an interrupt request; instruction register means coupled to said data bus means for temporarily storing any one of a plurality of software instructions, including a first instruction having a fixed code, received by said data bus means; gating means for operatively coupling said data bus means to said instruction register means; instruction decode means responsive to the contents of said instruction register means for controlling execution of said instruction; interrupt means responsive to both said interrupt request input signal and to said first instruction coupled to said gating means for producing a signal for inhibiting loading of the next instruction to be executed in response to either said interrupt request input signal or said first instruction; and said gating means including means responsive to said signal coupled to said instruction register means for forcing a second code having a plurality of bits which are the same as corresponding bits of said first code into said instruction register means in response to said interrupt request input signal.
Claim 2
Dependent Claim
191 words
A microprocessor comprising: a data bus means for transferring digital information; an interrupt request input conductor for conducting an interrupt request input signal representative of an interrupt request; instruction register means coupled to said data bus means for temporarily storing any one of a plurality of software instructions, including a first instruction having a fixed code, received by said data bus means; gating means for operatively coupling said data bus means to said instruction register means; instruction decode means responsive to the contents of said instruction register means for controlling execution of said instruction; interrupt means responsive to both said interrupt request input signal and to said first instruction coupled to said gating means for producing a signal for inhibiting loading of the next instruction to be executed in response to either said interrupt request input signal or said first instruction; and said gating means including means responsive to said signal coupled to said instruction register means for forcing a second code having a plurality of bits which are the same as corresponding bits of said first code into said instruction register means in response to said interrupt request input signal.
Claim 3
Dependent Claim
18 words
The microprocessor as recited in claim 1 wherein said second code is represented by the logical expression 00111110.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-07-18 | 1981-01-17 | 1981-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-07-18 | 1985-01-17 | 1985-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-07-18 | 1989-01-17 | 1989-07-19 | $7700.00 | Window Closed / Lapsed |