US4812967A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for controlling interrupts in a virtual machine system
Assignee: Hitachi Ltd
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Filing: 1986-03-07
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Granted: 1989-03-14
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Expires: 2006-03-07
Abstract
Abstract At an occurrence of an interrupt, each entry of the vector table of the vitrual machine monitor to be referenced by the hardware of the bare machine is loaded with an address of an interrupt processing program of the running virtual machine for an interrupt number associated with the entry. When the interrupt is allowed to be directly processed by the virtual machine, the virtual machine monitor is not activated, that is, the interrupt processing program of the vitual machine can immediately execute the necessary processing, which eliminates the overhead associated with the intervention of the virtual machine monitor. Moreover, the content of the system stack pointer is set to point to the stack of the running virtual machine. Consequently, the content of the registers to be saved for an interrupt processing are directly stored in the stack of the running virtual machine, and therefore the overhead caused because the stack of the virtual machine monitor is used is removed.
Inventors
- 👤 Toshio Hirosawa
- 👤 Jun'ichi Kurihara
- 👤 Shigemi Okumura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:00
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4843; G06F9/44; G06F9/455; G06F9/45533
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
279 words
An interrupt control method in a virtual machine system wherein a plurality of virtual machines are realized by selectively putting into execution, under control of a first control program, one of a plurality of second control programs respectively controlling execution of programs to be executed by said virtual machines, said first control program having a corresponding first vector table for holding physical addresses required to start interrupt processing programs included either in said first control program or in one of said second control programs under execution and said second control programs each having a corresponding second vector table for holding logical addresses indicative of interrupt processing programs included in each second control program, said method comprising the steps of: (i) generating physical addresses indicative of addresses of interrupt processing programs included in a selected second control program put into execution under control of said first control program, said generation being done based upon said logical addresses held by said second vector table corresponding to said selected second control program; (ii) writing the generated physical addresses into entries within said first vector table which are predetermined as entries for holding addresses required to start said interrupt processing programs included in said selected second control program; (iii) starting execution of said selected second control program after the second step (ii); (iv) reading out one of the addresses held by said first vector table corresponding to an interrupt processing program in response to a generated interrupt request; and (v) starting said interrupt processing program indicated by said read out address, irrespective of whether or not said interrupt processing program is included in said first control program or said selected second control program.
Claim 2
Dependent Claim
279 words
An interrupt control method in a virtual machine system wherein a plurality of virtual machines are realized by selectively putting into execution, under control of a first control program, one of a plurality of second control programs respectively controlling execution of programs to be executed by said virtual machines, said first control program having a corresponding first vector table for holding physical addresses required to start interrupt processing programs included either in said first control program or in one of said second control programs under execution and said second control programs each having a corresponding second vector table for holding logical addresses indicative of interrupt processing programs included in each second control program, said method comprising the steps of: (i) generating physical addresses indicative of addresses of interrupt processing programs included in a selected second control program put into execution under control of said first control program, said generation being done based upon said logical addresses held by said second vector table corresponding to said selected second control program; (ii) writing the generated physical addresses into entries within said first vector table which are predetermined as entries for holding addresses required to start said interrupt processing programs included in said selected second control program; (iii) starting execution of said selected second control program after the second step (ii); (iv) reading out one of the addresses held by said first vector table corresponding to an interrupt processing program in response to a generated interrupt request; and (v) starting said interrupt processing program indicated by said read out address, irrespective of whether or not said interrupt processing program is included in said first control program or said selected second control program.
Claim 3
Dependent Claim
50 words
An interrupt control method according to claim 1 wherein said first step (i) includes the step of adding an address value kept in said second vector table to a first address of a main memory area allocated to said selected second control program so as to determine the physical addresses.
Claim 4
Dependent Claim
108 words
An interrupt control method according to claim 1, wherein said first step (i) includes the step of accessing each of a plurality of entries in said second vector table corresponding to said selected second control program based on a start address of said second vector table of said selected second control program and one of a plurality of interrupt identification numbers predetermined for interrupt requests which should be processed by each of said interrupt processing programs included in said selected second control program; and wherein said second step (ii) includes the step of accessing each entry in said first vector table based on said one interrupt identification number.
Claim 5
Dependent Claim
36 words
An interrupt control method according to claim 3 wherein said fourth step (iv) includes the step of accessing an entry in said first vector table based on an interrupt number included in the generated interrupt request.
Claim 6
Dependent Claim
186 words
A virtual machine system having a plurality of virtual machines running in a bare machine under control of a control program, said control program including a plurality of instructions, said system comprising: (i) a memory area of a virtual machine of said plurality of virtual machines existing in a main memory of said bare machine, said memory area being subjected to processing and being continuously allocated; (ii) means to be operated at an execution of an instruction for adding a first address of the memory area of said virtual machine to a memory address of said bare machine which is generated at the execution of the instruction; (iii) means to be operated at an occurrence of an interrupt for inhibiting said addition of a first address of the memory area of said virtual machine and a memory address of said bare machine which is generated at the execution of the instruction; and (iv) means for releasing the inhibiting function performed by said means to be operated at an occurrence of an interrupt before control is returned to execution of an instruction after completion of interrupt processing.
Claim 7
Dependent Claim
186 words
A virtual machine system having a plurality of virtual machines running in a bare machine under control of a control program, said control program including a plurality of instructions, said system comprising: (i) a memory area of a virtual machine of said plurality of virtual machines existing in a main memory of said bare machine, said memory area being subjected to processing and being continuously allocated; (ii) means to be operated at an execution of an instruction for adding a first address of the memory area of said virtual machine to a memory address of said bare machine which is generated at the execution of the instruction; (iii) means to be operated at an occurrence of an interrupt for inhibiting said addition of a first address of the memory area of said virtual machine and a memory address of said bare machine which is generated at the execution of the instruction; and (iv) means for releasing the inhibiting function performed by said means to be operated at an occurrence of an interrupt before control is returned to execution of an instruction after completion of interrupt processing.
Claim 8
Dependent Claim
15 words
A virtual machine system according to claim 5 wherein said bare machine comprises a microprocessor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-13 | 1992-09-12 | 1993-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-13 | 1996-09-12 | 1997-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-13 | 2000-09-12 | 2001-03-14 | $7700.00 | Window Closed / Lapsed |