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US5050170A
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Apparatus for combining signals from first and second information processing elements
Assignee: Schlumberger Technologies Inc
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Filing: 1987-09-04
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Granted: 1991-09-17
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Expires: 2007-09-04
Abstract
Abstract A formatter for combining timing signals with data from an algorithmic pattern generator (APG). In the disclosed embodiment, the formatter receives address signals from an APG and timing signals from a timing unit. Each timing signal from the timing unit corresponds to an address signal received from the APG. The address and timing signals are communicated to a signal select unit wherein each timing signal selects its corresponding APG address signal. The selected APG address signal then is communicated to a signal combining unit which combines the APG address with its corresponding timing signal and generates leading edge and trailing edge marker pulses having a user-specified pulse width.
Inventors
- 👤 David G. Abdoo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:45
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31922; G01R31/31928
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
104 words
A circuit for combining signals from first and second information processing elements comprising: first input means for receiving a first signal from the first information processing element; second input means for receiving a second signal from the second information processing element; pulse forming means, coupled to the second input means, for generating a first pulse in response to the second signal; and pulse output means, coupled to the first input means and to the pulse forming means, for emitting a second pulse when a first signal is received from the first input means and the first pulse is received from the pulse forming means.
Claim 2
Dependent Claim
104 words
A circuit for combining signals from first and second information processing elements comprising: first input means for receiving a first signal from the first information processing element; second input means for receiving a second signal from the second information processing element; pulse forming means, coupled to the second input means, for generating a first pulse in response to the second signal; and pulse output means, coupled to the first input means and to the pulse forming means, for emitting a second pulse when a first signal is received from the first input means and the first pulse is received from the pulse forming means.
Claim 3
Dependent Claim
50 words
The circuit according to claim 1 wherein the first input means further comprises: selecting means, coupled to the pulse forming means and to the pulse output means, for selecting a first signal in response to the second signal and for emitting the selected first signal to the pulse output means.
Claim 4
Dependent Claim
37 words
The circuit according to claim 2 wherein the selected first signal is emitted from the selecting means for a prescribed time interval and the first pulse is emitted from the pulse forming means within the time interval.
Claim 5
Dependent Claim
28 words
The circuit according to claim 3 wherein a leading edge of the first pulse emitted from the pulse forming means occurs after the beginning of the time interval.
Claim 6
Dependent Claim
31 words
The circuit according to claim 4 wherein a time interval of the first pulse emitted from the pulse forming means is shorter than a time interval of the selected first signal.
Claim 7
Dependent Claim
47 words
The circuit according to claim 5 wherein the selected first signal is emitted to the pulse output means for a prescribed time interval, the time interval of the selected first signal being greater than the time interval of the first pulse emitted from the pulse forming means.
Claim 8
Dependent Claim
25 words
The circuit according to claim 6 wherein the pulse forming means further comprises means for selectively varying the width of the first pulse emitted therefrom.
Claim 9
Dependent Claim
126 words
The circuit according to claim 6 wherein the pulse forming means further comprises: first path means for communicating a first signal portion of the second signal along a first path; second path means for communicating a second signal portion of the second signal along a second path; delay means, coupled to the second path means, for delaying the communication of the second signal portion along the second path; and first pulse emitting means, coupled to the first path means and to the second path means, for receiving the first and second signal portions and for forming the first pulse, the width of the first pulse being a function of the time the first signal portion is received and the time the second signal portion is received.
Claim 10
Dependent Claim
41 words
The circuit according to claim 8 wherein the delay means further comprises means for selectively varying the amount by which the second signal portion is delayed for selectively varying the width of the first pulse emitted from the pulse forming means.
Claim 11
Dependent Claim
56 words
The circuit according to claim 6 wherein the pulse output means comprises: pulse combining means for receiving the selected first signal and the first pulse and for emitting a combined signal in response thereto; and second pulse generating means, coupled to the pulse combining means, for generating the second pulse in response to the combined signal.
Claim 12
Dependent Claim
57 words
The circuit according to claim 10 wherein the second pulse generating means further comprises: leading edge generating means for generating a leading edge signal for the second pulse; and trailing edge generating means, coupled to the leading edge generating means, for generating a trailing edge signal for the second pulse in response to the leading edge signal.
Claim 13
Dependent Claim
49 words
The circuit according to claim 11 wherein the second pulse generating means further comprises: leading edge delay means, disposed between the leading edge generating means and the trailing edge generating means, for delaying the leading edge signal being communicated to the trailing edge generating means by a prescribed amount.
Claim 14
Dependent Claim
28 words
The apparatus according to claim 12 wherein the leading edge delay means further comprises means for selectively varying the amount by which the leading edge signal is delayed.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-16 | 1995-03-18 | 1995-09-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-16 | 1999-03-18 | 1999-09-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-16 | 2003-03-18 | 2003-09-17 | $7700.00 | Window Closed / Lapsed |