Digital-to-analog converter with bit weight segmented arrays

Claim 2

An integrated circuit comprising a converter for converting a multi-bit digital signal to an analog signal, the converter comprising: means defining a first flow path for a reference current; current-to-voltage converting circuit means connected to the first flow path for producing a first bias voltage having a magnitude that depends upon the magnitude of the reference current; means defining a second flow path for an analog current, the magnitude of which defines the analog signal; first current-sourcing means biased by the first bias voltage for producing, in parallel, a first plurality of switchable currents that each mirror the reference current; first switching means controlled by the digital value of a low-order portion of the digital signal for selectively switching the first plurality of switchable currents to the second flow path so as to contribute unit steps to the analog signal; circuit means biased by the first bias voltage for producing a summed current having a magnitude that is a multiple of the magnitude of the reference current; circuit means responsive to the summed current for producing a second bias voltage; second current-sourcing means biased by the second bias voltage for producing, in parallel, a second plurality of switchable currents that each mirror the summed current; and second switching means controlled by the digital value of a higher-order portion of the digital signal for selectively switching the second plurality of switchable currents to the second flow path so as to contribute multi-unit steps to the analog signal.

Claim 3

An integrated circuit in accord with claim 1, wherein the circuit means for producing the summed current includes a plurality of current-sourcing means biased by the first bias voltage for producing, in parallel, a plurality of unswitched currents, and further includes means defining a summing junction into which all the unswitched currents flow.

Claim 4

An integrated circuit in accord with claim 2, wherein the current-sourcing means for producing the unswitched currents are positioned to form an array.

Claim 5

An integrated circuit in accord with claim 3, wherein the current-sourcing means for producing the switchable currents that mirror the reference current are positioned in the same array as the means for producing the unswitched currents.

Claim 6

An integrated circuit in accord with claim 1, wherein the converter is constructed with CMOS FETs, and wherein the current-to-voltage converting means includes a plurality of diode-connected FETs for producing the first bias voltage.

Claim 7

An integrated circuit in accord with claim 1 wherein the converter is constructed with CMOS FETs, and wherein the current-sourcing means for producing the unswitched currents comprise a plurality of FETs positioned in an array, and wherein a plurality of the diode-connected FETs are connected to a common conductor that extends across the array and is connected to the gate of each of the unswitched-current producing FETs.

Claim 8

An integrated circuit in accord with claim 1, wherein each current-sourcing means includes a plurality of FETs each operating in its saturation region as a voltage-to-current converting circuit.

Claim 9

An integrated circuit in accord with claim 7, wherein the type of FET that is incorporated in the first current-sourcing means is the same as the type of FET that is incorporated in the second current-sourcing means, and wherein the circuit means for producing the second bias voltage includes means for mirroring the summed current, and diode-connected FETs for converting the mirrored summed current to the voltage that constitutes the second bias voltage.

Claim 10

An integrated circuit in accord with claim 1, wherein the digital signal comprises eight binary bits, three bits of which constitute the low-order portion and the remaining five bits of which constitute the high-order portion.

Claim 11

An integrated circuit in accord with claim 9, wherein the number of switchable currents that each mirror the reference current is seven, and wherein the circuit means for producing the summed current comprises eight FETs each operating in its saturation region as a voltage-to-current converting circuit.

Claim 12

An integrated circuit in accord with claim 1, wherein the first and second switching means each include a plurality of level-shift circuits.

Claim 13

An integrated circuit in accord with claim 11, wherein each of the level-shift circuits includes three series-connected FETs.

Claim 14

A digital-to-analog converter embodied in a CMOS integrated circuit, the converter comprising: means defining a first flow path for a reference current; current-to-voltage converting circuit means comprising at least one diode-connected FET connected to the first flow path for producing a first bias voltage having a magnitude that depends upon the magnitude of the reference current; means defining a second flow path for an analog current, the magnitude of which defines the analog signal; first current-sourcing means comprising a plurality of FETs each operating in its saturation region as a voltage-to-current converting circuit and each converting the first bias voltage to a respective one of a first plurality of switchable currents that each mirror the reference current; first switching means controlled by the digital value of a low-order portion of the digital signal for selectively switching the first plurality of switchable currents to the second flow path so as to contribute unit steps to the analog signal; circuit means biased by the first bias voltage for producing a summed current having a magnitude that is a multiple of the magnitude of the reference current; circuit means biased by the summed current for producing a second bias voltage; second current-sourcing means comprising a plurality of FETs each operating in its saturation region as a voltage-to-current converter and each converting the second bias voltage to a respective one of a second plurality of switchable currents that each mirror the summed current; and second switching means controlled by the digital value of a higher-order portion of the digital signal for selectively switching the second plurality of switchable currents to the second flow path so as to contribute multi-unit steps to the analog signal.

Claim 15

A digital-to-analog converter embodied in a CMOS integrated circuit, the converter comprising: means defining a first flow path for a reference current; current-to-voltage converting circuit means comprising at least one diode-connected FET connected to the first flow path for producing a first bias voltage having a magnitude that depends upon the magnitude of the reference current; means defining a second flow path for an analog current, the magnitude of which defines the analog signal; first current-sourcing means comprising a plurality of FETs each operating in its saturation region as a voltage-to-current converting circuit and each converting the first bias voltage to a respective one of a first plurality of switchable currents that each mirror the reference current; first switching means controlled by the digital value of a low-order portion of the digital signal for selectively switching the first plurality of switchable currents to the second flow path so as to contribute unit steps to the analog signal; circuit means biased by the first bias voltage for producing a summed current having a magnitude that is a multiple of the magnitude of the reference current; circuit means biased by the summed current for producing a second bias voltage; second current-sourcing means comprising a plurality of FETs each operating in its saturation region as a voltage-to-current converter and each converting the second bias voltage to a respective one of a second plurality of switchable currents that each mirror the summed current; and second switching means controlled by the digital value of a higher-order portion of the digital signal for selectively switching the second plurality of switchable currents to the second flow path so as to contribute multi-unit steps to the analog signal.

Claim 16

A digital-to-analog converter in accord with claim 13, wherein the circuit means for producing the summed current includes a plurality of current-sourcing means controlled by the first bias voltage for producing, in parallel, a plurality of unswitched currents, and further includes means defining a summing node into which all the unswitched currents flow.

Claim 17

A digital-to-analog converter in accord with claim 14, wherein the current-sourcing means for producing the unswitched currents are positioned to form an array.

Claim 18

A digital-to-analog converter in accord with claim 15, wherein the current-sourcing means for producing the switchable currents that mirror the reference current are positioned in the array.

Claim 19

A digital-to-analog converter in accord with claim 13, wherein a plurality of diode-connected FETs operate as current-to-voltage converting circuits in the circuit means for producing the bias voltages.

Claim 20

A digital-to-analog converter in accord with claim 17, wherein the current-sourcing means for producing the unswitched currents are positioned to form an array, and wherein a plurality of the diode-connected FETs are connected to a common conductor extending across the array.

Claim 21

A digital-to-analog converter in accord with claim 17, wherein the current-sourcing means include a plurality of FETs each operating in its saturation region as a voltage-to-current converting circuit.

Claim 22

A digital-to-analog converter in accord with claim 19, wherein the type of FET that is incorporated in the first current-sourcing means is the same as the type of FET that is incorporated in the second current-sourcing means, and wherein the circuit means for producing the second bias voltage includes means for mirroring the summed current, and diode-connected FETs for converting the mirrored summed current to the voltage that constitutes the second bias voltage.

Claim 23

A digital-to-analog converter in accord with claim 13, wherein the digital signal comprises eight binary bits, three bits of which constitute the low-order portion and the remaining five bits of which constitute the high-order portion.

Claim 24

A digital-to-analog converter in accord with claim 21, wherein the number of switchable currents that each-mirror the reference current is seven, and wherein the circuit means for producing a summed current comprises eight FETs each operating in its saturation region as a voltage-to-current converting circuit.

Claim 25

A digital-to-analog converter embodied in a CMOS integrated circuit, the converter comprising: means defining a first flow path for a reference current; current-to-voltage converting circuit means comprising a plurality of diode-connected FETs connected to the first flow path for producing a first bias voltage having a magnitude that depends upon the magnitude of the reference current; means defining a second flow path for an analog current, the magnitude of which defines the analog signal; first current-sourcing means comprising a plurality of FETs each operating in its saturation region as a voltage-to-current converting circuit and each converting the first bias voltage to a respective one of a first plurality of switchable currents that each mirror the reference current; first differential switching means controlled by the digital value of a low-order portion of the digital signal for selectively switching the first plurality of switchable currents to the second flow path so as to contribute unit steps to the analog signal; circuit means comprising a plurality of FETs each operating in its saturation region as a voltage-to-current converting circuit and each converting the first bias voltage to a respective one of a plurality of unswitched currents that each mirror the reference current; diode-connected-FET circuit means connected as a summing node in which the unswitched currents combine to define a summed current having a magnitude that is a multiple of the magnitude of the reference current, the diode-connected-FET circuit means being controlled by the summed current for producing a second bias voltage; second current-sourcing means comprising a plurality of FETs each operating in its saturation region as a voltage-to-current converting circuit and each converting the second bias voltage to a respective one of a second plurality of switchable currents that each mirror the summed current; and second switching means controlled by the digital value of a higher-order portion of the digital signal for selectively switching the second plurality of switchable currents to the second flow path so as to contribute multi-unit steps to the analog signal.

Claim 26

A digital-to-analog converter embodied in a CMOS integrated circuit, the converter comprising: means defining a first flow path for a reference current; current-to-voltage converting circuit means comprising a plurality of diode-connected FETs connected to the first flow path for producing a first bias voltage having a magnitude that depends upon the magnitude of the reference current; means defining a second flow path for an analog current, the magnitude of which defines the analog signal; first current-sourcing means comprising a plurality of FETs each operating in its saturation region as a voltage-to-current converting circuit and each converting the first bias voltage to a respective one of a first plurality of switchable currents that each mirror the reference current; first differential switching means controlled by the digital value of a low-order portion of the digital signal for selectively switching the first plurality of switchable currents to the second flow path so as to contribute unit steps to the analog signal; circuit means comprising a plurality of FETs each operating in its saturation region as a voltage-to-current converting circuit and each converting the first bias voltage to a respective one of a plurality of unswitched currents that each mirror the reference current; diode-connected-FET circuit means connected as a summing node in which the unswitched currents combine to define a summed current having a magnitude that is a multiple of the magnitude of the reference current, the diode-connected-FET circuit means being controlled by the summed current for producing a second bias voltage; second current-sourcing means comprising a plurality of FETs each operating in its saturation region as a voltage-to-current converting circuit and each converting the second bias voltage to a respective one of a second plurality of switchable currents that each mirror the summed current; and second switching means controlled by the digital value of a higher-order portion of the digital signal for selectively switching the second plurality of switchable currents to the second flow path so as to contribute multi-unit steps to the analog signal.