US4635038A
Expired / Lapsed
US
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CMOS-transistor-based digital-to-analog converter
Assignee: Advanced Micro Devices Inc
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Filing: 1985-11-08
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Granted: 1987-01-06
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Expires: 2005-11-08
Abstract
Abstract A digital-to-analog converter for converting a digital signal having a plurality of binary bits into an analog output signal includes an R-2R ladder network forming a plurality of switching cells corresponding in number to the number of the binary bits. Each switching cell is formed of first, second and third pairs of CMOS transistors defining cross resistances of the ladder network and of a fourth pair of CMOS transistors defining a series resistance of ladder network. A pair of differential circuits drives each switching cell to control switching symmetry and conversion speed.
Inventors
- 👤 John M. Wincn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 09:56
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/74; H03M1/742; H03M1/747
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
359 words
A digital-to-analog converter for converting a digital signal having a plurality of binary bits into an analog output signal comprising: an R-2R ladder network forming a plurality of switching cells corresponding in number to the number of said binary bits; each switching cell being formed of first, second, and third pairs of CMOS transistors defining cross resistances of the ladder network and of a fourth pair of CMOS transistors defining a series resistance of the ladder network, each of first through fourth pairs including a P-channel MOS transistor and an N-channel MOS transistor having the drain of the NMOS transistor connected to the source of the PMOS transistor and the source of the NMOS transistor connected to the drain of the PMOS transistor; the NMOS drain and PMOS source of said first pair being connected to the NMOS drain and PMOS source of said fourth pair to define a ladder node, the NMOS source and PMOS drain of said first pair being connected to the NMOS drain and PMOS source of said second pair and to the NMOS drain and PMOS source of said third pair, the NMOS source and PMOS drain of said second pair being coupled to a common line and the NMOS source and PMOS drain of said third pair being coupled to a common output current summing line, the NMOS source and PMOS drain of said fourth pair being connected to a next ladder node of a succeeding switching cell; the gates of said P-channel transistors in said first and fourth pairs being connected to a first supply voltage for rendering them to be constantly conductive and the gates of said N-channel transistors in said first and fourth pairs being connected to a second supply voltage for rendering them to be constantly conductive; and switching means having inputs responsive to a respective binary bit of said digital signal and having outputs connected to the gates of the P-channel and N-channel transistors in said second and third pairs for selectively turning on or off said second pair and turning off or on said third pair respectively dependent upon the logic state of said respective binary bit.
Claim 2
Dependent Claim
359 words
A digital-to-analog converter for converting a digital signal having a plurality of binary bits into an analog output signal comprising: an R-2R ladder network forming a plurality of switching cells corresponding in number to the number of said binary bits; each switching cell being formed of first, second, and third pairs of CMOS transistors defining cross resistances of the ladder network and of a fourth pair of CMOS transistors defining a series resistance of the ladder network, each of first through fourth pairs including a P-channel MOS transistor and an N-channel MOS transistor having the drain of the NMOS transistor connected to the source of the PMOS transistor and the source of the NMOS transistor connected to the drain of the PMOS transistor; the NMOS drain and PMOS source of said first pair being connected to the NMOS drain and PMOS source of said fourth pair to define a ladder node, the NMOS source and PMOS drain of said first pair being connected to the NMOS drain and PMOS source of said second pair and to the NMOS drain and PMOS source of said third pair, the NMOS source and PMOS drain of said second pair being coupled to a common line and the NMOS source and PMOS drain of said third pair being coupled to a common output current summing line, the NMOS source and PMOS drain of said fourth pair being connected to a next ladder node of a succeeding switching cell; the gates of said P-channel transistors in said first and fourth pairs being connected to a first supply voltage for rendering them to be constantly conductive and the gates of said N-channel transistors in said first and fourth pairs being connected to a second supply voltage for rendering them to be constantly conductive; and switching means having inputs responsive to a respective binary bit of said digital signal and having outputs connected to the gates of the P-channel and N-channel transistors in said second and third pairs for selectively turning on or off said second pair and turning off or on said third pair respectively dependent upon the logic state of said respective binary bit.
Claim 3
Dependent Claim
51 words
A digital-to-analog converter as claimed in claim 1, wherein said switching means comprises first and second differential driver circuits, each of said first and second differential driver circuits having a first input responsive to said respective binary bit and a second input responsive to the complement of said respective binary bit.
Claim 4
Dependent Claim
45 words
A digital-to-analog converter as claimed in claim 2, wherein said first differential driver circuit has a first output connected to the gate of the P-channel transistor in said second pair and a second output connected to the gate of the P-channel in said third pair.
Claim 5
Dependent Claim
46 words
A digital-to-analog converter as claimed in claim 3, wherein said second differential driver circuit has a first output connected to the gate of the N-channel transistor in said second pair and a second output connected to the gate of the N-channel transistor in said third pair.
Claim 6
Dependent Claim
22 words
A digital-to-analog converter as claimed in claim 3, wherein said first differential driver circuit is formed of P-channel and N-channel MOS transistors.
Claim 7
Dependent Claim
22 words
A digital-to-analog converter as claimed in claim 4, wherein said second differential driver circuit is formed of P-channel and N-channel MOS transistors.
Claim 8
Dependent Claim
25 words
A digital-to-analog converter as claimed in claim 1, wherein said converter is formed as part of single silicon semiconductor chip of a monolithic integrated circuit.
Claim 9
Dependent Claim
37 words
A digital-to-analog converter as claimed in claim 2, further comprising a bias generator network for supplying a first bias voltage to said first differential driver circuit and a second bias voltage to said second differential driver circuit.
Claim 10
Dependent Claim
28 words
A digital-to-analog converter as claimed in claim 8, wherein said bias network comprises a P-channel MOS transistor, a first N-channel MOS transistor and a second N-channel MOS transistor.
Claim 11
Dependent Claim
97 words
A digital-to-analog converter as claimed in claim 9, wherein said P-channel transistor has its source connected to said first supply voltage and its gate and drain connected together, said first N-channel transistor having its gate and drain connected together and to the drain of said P-channel transistor, said second N-channel transistor having its gate and drain connected together and its source connected to a ground potential, the common drains of said P-channel transistor and said first N-channel transistor defining said first bias voltage, the common drain and gate of said second N-channel transistor defining said second voltage.
Claim 12
Dependent Claim
302 words
In a digital-to-analog converter for converting a digital signal having a plurality of binary bits into an analog output signal, the improvement comprising: an R-2R ladder network forming a plurality of switching cells corresponding in number to the number of said binary bits; each switching cell being formed of first, second and third pairs of CMOS transistors defining cross resistances of the ladder network and of a fourth pair of CMOS transistors defining a series resistance of the ladder network, each of said first through fourth pairs including a P-channel MOS transistor and an N-channel MOS transistor having the drain of the NMOS transistor connected to the source of the PMOS transistor and the source of the NMOS transistor connected to the drain of the PMOS transistor; the NMOS drain and PMOS source of said first pair being connected to the NMOS drain and PMOS source of said fourth pair to define a ladder node, the NMOS source and PMOS drain of said first pair being connected to the NMOS drain and PMOS source of said second pair and to the NMOS drain and PMOS source of said third pair, the NMOS source and PMOS drain of said second pair being coupled to a common line and the NMOS source and PMOS drain of said third pair being coupled to a common output current summing line, the NMOS source and PMOS drain of said fourth pair being connected to a next ladder node of a succeeding switching cell; and the gates of said P-channel transistors in said first and fourth pairs being connected to a first supply voltage for rendering them to be constantly conductive and the gates of said N-channel transistors in said first and fourth pairs being connected to a second supply voltage for rendering them to be constantly conductive.
Claim 13
Dependent Claim
302 words
In a digital-to-analog converter for converting a digital signal having a plurality of binary bits into an analog output signal, the improvement comprising: an R-2R ladder network forming a plurality of switching cells corresponding in number to the number of said binary bits; each switching cell being formed of first, second and third pairs of CMOS transistors defining cross resistances of the ladder network and of a fourth pair of CMOS transistors defining a series resistance of the ladder network, each of said first through fourth pairs including a P-channel MOS transistor and an N-channel MOS transistor having the drain of the NMOS transistor connected to the source of the PMOS transistor and the source of the NMOS transistor connected to the drain of the PMOS transistor; the NMOS drain and PMOS source of said first pair being connected to the NMOS drain and PMOS source of said fourth pair to define a ladder node, the NMOS source and PMOS drain of said first pair being connected to the NMOS drain and PMOS source of said second pair and to the NMOS drain and PMOS source of said third pair, the NMOS source and PMOS drain of said second pair being coupled to a common line and the NMOS source and PMOS drain of said third pair being coupled to a common output current summing line, the NMOS source and PMOS drain of said fourth pair being connected to a next ladder node of a succeeding switching cell; and the gates of said P-channel transistors in said first and fourth pairs being connected to a first supply voltage for rendering them to be constantly conductive and the gates of said N-channel transistors in said first and fourth pairs being connected to a second supply voltage for rendering them to be constantly conductive.
Claim 14
Dependent Claim
70 words
In a digital-to-analog converter as claimed in claim 11, further comprising switching means having inputs responsive to a respective binary bit of said digital signal and having outputs connected to the gates of the P-channel and N-channel transistors in said second and third pairs for selectively turning on or off said second pair and turning off or on said third pair dependent upon the logic of said respective binary bit.
Claim 15
Dependent Claim
52 words
In a digital-to-analog converter as claimed in claim 12, wherein said switching means comprises first and second differential driver circuits, each of said first and second differential driver circuits having a first input responsive to said respective binary bit and a second input responsive to the complement of said respective binary bit.
Claim 16
Dependent Claim
46 words
In a digital-to-analog converter as claimed in claim 13, wherein said first differential driver circuit has a first output connected to the gate of the P-channel transistor in said second pair and a second output connected to the gate of the P-channel in said third pair.
Claim 17
Dependent Claim
47 words
In a digital-to-analog converter as claimed in claim 14, wherein said second differential driver circuit has a first output connected to the gate of the N-channel transistor in said second pair and a second output connected to the gate of the N-channel transistor in said third pair.
Claim 18
Dependent Claim
23 words
In a digital-to-analog converter as claimed in claim 15, wherein said first differential driver circuit is formed of P-channel and N-channel MOS transistors.
Claim 19
Dependent Claim
23 words
In a digital-to-analog converter as claimed in claim 16, wherein said second differential driver circuit is formed of P-channel and N-channel MOS transistors.
Claim 20
Dependent Claim
26 words
In a digital-to-analog converter as claimed in claim 12, wherein said converter is formed as part of single silicon semiconductor chip of a monolithic integrated circuit.
Claim 21
Dependent Claim
38 words
In a digital-to-analog converter as claimed in claim 13, further comprising a bias generator network for supplying a first bias voltage to said first differential driver circuit and a second bias voltage to said second differential driver circuit.
Claim 22
Dependent Claim
29 words
In a digital-to-analog converter as claimed in claim 19, wherein said bias network comprises a P-channel MOS transistor, a first N-channel MOS transistor and a second N-channel MOS transistor.
References Cited (Backward Citations)
US4415883A
Cited
US4336527A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-05 | 1990-07-07 | 1991-01-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-05 | 1994-07-07 | 1995-01-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-05 | 1998-07-07 | 1999-01-06 | $7700.00 | Window Closed / Lapsed |