Cyclic group processing with internal priority

Claim 1

A computing device comprising a priority circuit for transferring one of a plurality of interrogation signals coming in from a number of lines in accordance with a given priority, in a cyclic order of succession while maintaining the priority in a group, said number of lines being arranged in a numbeR of different groups of lines, in which each interrogation signal and the inverses thereof of higher priority in the group are applied in each group to first respective inputs of a logic (NOT)-AND gate, a further respective input of each said logic (NOT)-AND gate in the group connected to the output of the preceding group, each group including an additional (NOT)-AND gate, one input of which is connected to said output of the preceding group and further inputs of which are connected to terminal means for providing the inverses of the interrogation signals, one of said groups including the output of each (NOT)-AND gate associated therewith connected to an input of a (n+1) inputs of a 1-out-of(n+2) position device, wherein n is the number of lines in one group, and means connecting the (n+2)th input of the 1-out-of(n+2) position device of one group to the output of the next following group for blocking said one group from interrogation signals during adjustment of a reset position.