US4370746A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory address selector
Assignee: International Business Machines Corp
•
Filing: 1980-12-24
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Granted: 1983-01-25
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Expires: 2000-12-24
Abstract
Abstract A testing apparatus, having an address generator for providing address signals to a test device and to a reference device, is provided with a programmable mask for passing only selected least significant X and Y address bits to the reference device.
Inventors
- 👤 Robert E. Jones
- 👤 Donald H. Wood
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:37
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/56; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/3193
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
110 words
In a testing apparatus of the type including a standard device for providing an output in response to N address signals received on N address input lines, a test device for providing an output in response to address signals received on a plurality of address lines, an address generator for providing address signals to said standard and test devices, and means for comparing the outputs from said two devices, the improvement comprising: said address generating means providing M address signals on M address output lines, M≧N; and programmable masking means for selecting N of said M address signals to be supplied as the N address signals to said standard device.
Claim 2
Dependent Claim
110 words
In a testing apparatus of the type including a standard device for providing an output in response to N address signals received on N address input lines, a test device for providing an output in response to address signals received on a plurality of address lines, an address generator for providing address signals to said standard and test devices, and means for comparing the outputs from said two devices, the improvement comprising: said address generating means providing M address signals on M address output lines, M≧N; and programmable masking means for selecting N of said M address signals to be supplied as the N address signals to said standard device.
Claim 3
Dependent Claim
48 words
A testing apparatus as defined in claim 1, wherein said programmable masking means comprises: a plurality of gates each of which passes an address signal from said address generator in response to a respective enabling signal; and means for selectively providing enabling signals to said plurality of gates.
Claim 4
Dependent Claim
18 words
A testing apparatus as defined in claim 2, wherein said standard and test devices are memory array devices.
Claim 5
Dependent Claim
88 words
A testing apparatus as defined in claim 3, wherein said address generator provides a plurality of X address signals and a plurality Y address signals and said plurality of gates are connected in pairs with one gate in each pair receiving a respective X address signal from said address generator and one gate in each pair receiving a Y address signal from said address generator, the outputs of the gates in each pair being coupled together to provide one of said N address signals to said standard device.
Claim 6
Dependent Claim
51 words
A testing apparatus as defined in claim 4, wherein said gates are tri-state gates and a pull-up resistor is coupled to the outputs of each gate pair whereby the address signal provided by said gate pair will assume a known value when neither of the gates in said pair is enabled.
Claim 7
Dependent Claim
64 words
A testing apparatus as defined in claim 4, wherein said X address signals are designated X 0 -X I and said Y address signals are designated Y 0 -Y I , and said X and Y address signals are paired in reverse numerical order with signals X 0 -X I being combined in said gate pairs with signals Y I -Y 0 , respectively.
Claim 8
Dependent Claim
20 words
A testing apparatus as defined in claim 4, wherein said gates are emitter coupled logic (ECL) gates having dottable outputs.
Claim 9
Dependent Claim
28 words
A testing apparatus as defined in claim 4, further comprising AND logic means for providing an output signal when both gates in any one gate pair are enabled.
Claim 10
Dependent Claim
67 words
A testing apparatus as defined in any one of claims 2-7, wherein said means for selectively providing said enabling signals comprises: latch means for receiving enabling data and storing said enabling data in response to a load signal, said latch means providing enabling signals at its output in accordance with said enabling data; and control means for providing said data and load signals to said latch means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-01-24 | 1986-07-26 | 1987-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-01-24 | 1990-07-26 | 1991-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-01-24 | 1994-07-26 | 1995-01-25 | $7700.00 | Window Closed / Lapsed |