US4450560A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Tester for LSI devices and memory devices
Assignee: Teradyne Inc
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Filing: 1981-10-09
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Granted: 1984-05-22
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Expires: 2001-10-09
Abstract
Abstract A single tester tests both LSI and memory devices by storing test signals and standards for the pins of LSI devices in a storage element, providing test signals and standards for the data pins of memory devices from a generator, and selectably routing the test signals and standards from the storage element for LSI testing and from the generator for memory testing; format and timing information for each test signal and standard (for LSI testing) or for groups of test signals and standards (for memory testing) is stored in a second storage element and addresses corresponding to each test signal and standard (for LSI testing) or to each group of test signals and standards (for memory testing) and selectably provided to the second storage element.
Inventors
- 👤 George W. Conner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:27
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/56; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31908; G01R31/31917; G01R31/31919
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
156 words
Apparatus for testing LSI and memory devices by injecting test signals and comparing resulting output signals with standards, said devices each having a multiplicity of pins, said pins of said memory devices comprising address pins and data pins, said apparatus comprising: a sequence controller for sequencing the injections of said test signals and the comparisons of said resulting output signals with said standards, a storage element for storing said test signals and said standards for said LSI devices, a generator for generating said test signals and said standards for said memory devices, source switching circuitry responsive to said sequence controller, said source switching circuitry being connected to selectably route said test signals and said standards for said LSI devices from said storage element to said pins, or said test signals and said standards for said memory devices from said generator to said data pins, and a comparator for comparing said resulting output signals with said standards.
Claim 2
Dependent Claim
156 words
Apparatus for testing LSI and memory devices by injecting test signals and comparing resulting output signals with standards, said devices each having a multiplicity of pins, said pins of said memory devices comprising address pins and data pins, said apparatus comprising: a sequence controller for sequencing the injections of said test signals and the comparisons of said resulting output signals with said standards, a storage element for storing said test signals and said standards for said LSI devices, a generator for generating said test signals and said standards for said memory devices, source switching circuitry responsive to said sequence controller, said source switching circuitry being connected to selectably route said test signals and said standards for said LSI devices from said storage element to said pins, or said test signals and said standards for said memory devices from said generator to said data pins, and a comparator for comparing said resulting output signals with said standards.
Claim 3
Dependent Claim
197 words
Apparatus for testing LSI and memory devices by injecting test signals and comparing resulting output signals with standards, said devices each having a multiplicity of pins, said pins of said memory devices comprising address pins and data pins, said apparatus comprising: a sequence controller for sequencing the injections of said test signals and the comparisions of said resulting output signals with said standards, a format and timing generator for generating format and timing information corresponding to said test signals and said standards, a sequence generator for causing said format and timing generator to provide updated format and timing information corresponding to each of said test signals and said standards for testing said LSI devices, a group sequence generator for causing said format and timing generator to provide updated format and timing information corresponding to groups of said test signals and said standards for testing said memory devices, and a mode controller responsive to said sequence controller for selectably activating either said sequence generator or said group sequence generator for testing respectively said LSI devices or said memory devices, an injector for injecting said test signals, and a comparator for comparing said resulting output signals with said standards.
Claim 4
Dependent Claim
197 words
Apparatus for testing LSI and memory devices by injecting test signals and comparing resulting output signals with standards, said devices each having a multiplicity of pins, said pins of said memory devices comprising address pins and data pins, said apparatus comprising: a sequence controller for sequencing the injections of said test signals and the comparisions of said resulting output signals with said standards, a format and timing generator for generating format and timing information corresponding to said test signals and said standards, a sequence generator for causing said format and timing generator to provide updated format and timing information corresponding to each of said test signals and said standards for testing said LSI devices, a group sequence generator for causing said format and timing generator to provide updated format and timing information corresponding to groups of said test signals and said standards for testing said memory devices, and a mode controller responsive to said sequence controller for selectably activating either said sequence generator or said group sequence generator for testing respectively said LSI devices or said memory devices, an injector for injecting said test signals, and a comparator for comparing said resulting output signals with said standards.
Claim 5
Dependent Claim
120 words
The apparatus of claim 1 further comprising: a format and timing generator for generating format and timing information corresponding to said test signals and standards, a sequence generator for causing said format and timing generator to provide updated format and timing information corresponding to each of said test signals and said standards for testing said LSI devices, a group sequence generator for causing said format and timing generator to provide updated format and timing information corresponding to groups of said test signals and standards for testing said memory devices, and a mode controller responsive to said sequence controller for selectably activating either said sequence generator or said group sequence generator for testing respectively said LSI devices or said memory devices.
Claim 6
Dependent Claim
42 words
The apparatus of claim 2 or 3 wherein said format and timing generator comprises a format memory for storing format information, and a format address memory responsive to said sequence controller for storing addresses corresponding to the locations in said format memory.
Claim 7
Dependent Claim
55 words
The apparatus of claim 2 or 3 wherein said format and timing generator comprises a timing memory for storing timing information, a timing generator for providing timing pulses in accordance with said timing information, and a timing address memory responsive to said sequence controller for storing addresses corresponding to the locations in said timing memory.
Claim 8
Dependent Claim
66 words
The apparatus of claim 1, 2 or 3 further comprising a comparator for providing error signals when said output signals differ from said standards, and error processing circuitry connected to selectably store said error signals as a map corresponding to the memory locations in said memory devices, or as sequences of said error signals and said test signals corresponding to said pins of said LSI devices.
Claim 9
Dependent Claim
55 words
The apparatus of claim 8 wherein said error processing circuitry comprises a fail proceessor responsive to said comparator, a fail sequence memory responsive to said sequence controller and to said fail processor for storing said sequences, and a fail map memory responsive to said fail processor and to said sequence controller for storing said map.
Claim 10
Independent Claim
141 words
A method of testing LSI devices and memory devices by injecting test signals and comparing resulting output signals with standards, said devices each having a multiplicity of pins, said pins of said memory devices comprising address pins and data pins, said method comprising: storing said test signals and standards for said LSI devices in a storage element, when said device is an LSI device, triggering a selector to route said test signals and said standards from said storage element to said pins, when said device is a memory device, causing a generator to generate said test signals and said standards, and simultaneously triggering said selector to route said test signals and said standards to said data pins, said selector being triggered for testing LSI devices and memory devices in any desired order, and comparing said resulting output signals with said standards.
Claim 11
Independent Claim
141 words
A method of testing LSI devices and memory devices by injecting test signals and comparing resulting output signals with standards, said devices each having a multiplicity of pins, said pins of said memory devices comprising address pins and data pins, said method comprising: storing said test signals and standards for said LSI devices in a storage element, when said device is an LSI device, triggering a selector to route said test signals and said standards from said storage element to said pins, when said device is a memory device, causing a generator to generate said test signals and said standards, and simultaneously triggering said selector to route said test signals and said standards to said data pins, said selector being triggered for testing LSI devices and memory devices in any desired order, and comparing said resulting output signals with said standards.
Claim 12
Independent Claim
181 words
A method of testing LSI devices and memory devices by injecting test signals and comparing resulting output signals with standards, said devices each having a multiplicity of pins, said method comprising: storing format and timing information corresponding to each of said test signals and said standards for said LSI devices in a storage element, storing format and timing information corresponding to groups of said test signals and said standards for said memory devices in said storage element, when said device is an LSI device, generating an address corresponding to each of said test signals and said standards, and simultaneously triggering a selector to route each said address to said storage element, when said device is a memory device, generating an address corresponding to each of said groups of said test signals and said standards, and simultaneously triggering a selector to route each said address to said storage element, said addresses being generated and said selector being triggered for testing LSI devices and memory devices in any desired order, injecting said test signals, and comparing said resulting output signals with said standards.
Claim 13
Independent Claim
181 words
A method of testing LSI devices and memory devices by injecting test signals and comparing resulting output signals with standards, said devices each having a multiplicity of pins, said method comprising: storing format and timing information corresponding to each of said test signals and said standards for said LSI devices in a storage element, storing format and timing information corresponding to groups of said test signals and said standards for said memory devices in said storage element, when said device is an LSI device, generating an address corresponding to each of said test signals and said standards, and simultaneously triggering a selector to route each said address to said storage element, when said device is a memory device, generating an address corresponding to each of said groups of said test signals and said standards, and simultaneously triggering a selector to route each said address to said storage element, said addresses being generated and said selector being triggered for testing LSI devices and memory devices in any desired order, injecting said test signals, and comparing said resulting output signals with said standards.
Claim 14
Dependent Claim
149 words
The method of claim 8 further comprising storing format and timing information corresponding to each of said test signals and said standards for said LSI devices in a further storage element, storing format and timing information corresponding to groups of said test signals and said standards for said memory devices in said further storage element, when said device is an LSI device, generating an address corresponding to each of said test signals and said standards, and simultaneously triggering a selector to route each said address to said further storage element, and when said device is a memory device, generating an address corresponding to each of said groups of said test signals and said standards, and simultaneously triggering a selector to route each said address to said further storage element, said addresses being generated and said selector being triggered for testing LSI devices and memory devices in any desired order.
Claim 15
Independent Claim
231 words
A method of testing LSI devices having memory portions and non-memory portions by injecting test signals and comparing resulting output signals with standards, said devices each having a multiplicity of pins, said method comprising storing said test signals and standards for said non-memory portions in a first storage element, storing format and timing information corresponding to each of said test signals and standards for said non-memory portions in a second storage element, storing format and timing information corresponding to groups of said test signals and said standards for said memory portions in said second storage element, triggering a selector to route said test signals and said standards from said first storage element to said pins of said non-memory portions, generating an address corresponding to each of said test signals and said standards for said non-memory portions, and simultaneously triggering a selector to route each said address to said second storage element, causing a generator to generate said test signals and said standards for said memory portions, and simultaneously triggering said selector to route said test signals and said standards to the data pins of said memory portions, generating an address corresponding to each of said groups of said test signals and said standards for said memory portions, and simultaneously triggering a selector to route each said address to said second storage element, and comparing said resulting output signals with said standards.
Claim 16
Independent Claim
231 words
A method of testing LSI devices having memory portions and non-memory portions by injecting test signals and comparing resulting output signals with standards, said devices each having a multiplicity of pins, said method comprising storing said test signals and standards for said non-memory portions in a first storage element, storing format and timing information corresponding to each of said test signals and standards for said non-memory portions in a second storage element, storing format and timing information corresponding to groups of said test signals and said standards for said memory portions in said second storage element, triggering a selector to route said test signals and said standards from said first storage element to said pins of said non-memory portions, generating an address corresponding to each of said test signals and said standards for said non-memory portions, and simultaneously triggering a selector to route each said address to said second storage element, causing a generator to generate said test signals and said standards for said memory portions, and simultaneously triggering said selector to route said test signals and said standards to the data pins of said memory portions, generating an address corresponding to each of said groups of said test signals and said standards for said memory portions, and simultaneously triggering a selector to route each said address to said second storage element, and comparing said resulting output signals with said standards.
References Cited (Backward Citations)
US2905930A
Cited
US3235849A
Cited
US3311890A
Cited
US3474421A
Cited
US3659088A
Cited
US3805243A
Cited
US3739349A
Cited
US3873817A
Cited
US3781829A
Cited
US3832535A
Cited
US3916306A
Cited
US4195779A
Cited
US4099259A
Cited
US4137562A
Cited
US4195343A
Cited
US4216539A
Cited
US4287594A
Cited
US4249173A
Cited
US4380068A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-22 | 1987-11-21 | 1988-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-22 | 1991-11-21 | 1992-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-22 | 1995-11-21 | 1996-05-22 | $7700.00 | Window Closed / Lapsed |