Function test evaluation apparatus for evaluating a function test of a logical circuit

Claim 1

A function test evaluation apparatus for evaluating the functioning of an integrated logic circuit comprising: a control section including a main memory for storing input test information to be supplied to an integrated circuit to be tested and expected value information to be compared with real value information outputted from the integrated circuit after testing, a central processing element for performing various controls; a plurality of memory means for addressably storing the input test information supplied from said main memory of said control section and the expected value information and for outputting said input test information and said expected value information when addressed; a plurality of write circuit means for addressably writing the input test information and the expected value information outputted from said main memory into said plurality of memory means; an address control circuit means for simultaneously supplying the same address information through a plurality of said memory means; a plurality of data register means for storing said input test information and said expected value information outputted from said memory means when said memory means are addressed by said control circuit and for outputting said stored information in parallel; parallel-to-serial converting means for receiving said information outputted by said data register means and for converting said received information into serial data; a pattern format control circuit for receiving and shaping said serial data and supplying said shaped data to said integrated circuit to be tested; and judgment circuit means for comparing the expected value information outputted serially from said parallel-to-serial converting circuit with the information outputted from said integrated circuit after said integrated circuit has been supplied with said input test information.