Microinstruction address modification and branch system

Claim 2

In a data processing system wherein macroinstructions containing OP-codes, address-condition signals, and addresses, are interpreted through the use of at least one microinstruction memory, a microbranch control comprising: first means for controlling the address selection of a microinstruction from said microinstruction memory; second means for receiving a selected microinstruction read from said microinstruction memory and for producing corresponding micro-output signals; third means for producing microbranch control signals in response to predetermined sets of said micro-output signals; and fourth means responsive to said address-condition signals and to said microbranch control signals for controlling said first means to modify the contents of said microaddress register as a direct logical function of said address-condition signals.

Claim 3

In a computer system wherein main memory instructions defining arithmetic operations are translated through the use of at least one ROM, containing a related set of microinstructions for each main memory instruction, an improved branch device for controlling the address of microinstruction selection from said ROM said device comprising: ROM address means for controlling the selection of a microinstruction from said ROM ROM output means for producing ROM output signals corresponding to the selected microinstruction; micro-OP decoding means for translating certain portions of said microinstruction into branch micro-OPS; first logic responsive to branch-condition input signals and to said ROM output signals for producing ROM address modifying signals; and second logic means for controlling said ROM address means to branch directly to the next ROM microinstruction address as a direct logical function of all branch-condition input signals related to the decoded related portion of said microinstruction specifying the corresponding branch micro-OP.

Claim 4

In a computer system wherein main memory instructions defining arithmetic operations are translated through the use of at least one ROM, containing a related set of microinstructions for each main memory instruction, an improved branch device for controlling the address of microinstruction selection from said ROM said device comprising: ROM address means for controlling the selection of a microinstruction from said ROM ROM output means for producing ROM output signals corresponding to the selected microinstruction; micro-OP decoding means for translating certain portions of said microinstruction into branch micro-OPS; first logic responsive to branch-condition input signals and to said ROM output signals for producing ROM address modifying signals; and second logic means for controlling said ROM address means to branch directly to the next ROM microinstruction address as a direct logical function of all branch-condition input signals related to the decoded related portion of said microinstruction specifying the corresponding branch micro-OP.

Claim 5

A microprogram address modification system comprising: a first device for storing the present microaddress; a second device for receiving predetermined sets of condition signals C1 ... Cn and the microbranch code from the microinstruction read from said present microaddress, each predetermined set of condition signals being related to a particular set of program branches; a third device for developing address modification signals as a function of said sets of condition signals and said microbranch code; and a fourth device for introducing said modification signals into said present microaddress at bit position designated by said microbranch code to form a new microaddress constituting the next microaddress for reading the next microinstruction.

Claim 6

A microprogram address modification system comprising: a first device for storing the present microaddress; a second device for receiving predetermined sets of condition signals C1 ... Cn and the microbranch code from the microinstruction read from said present microaddress, each predetermined set of condition signals being related to a particular set of program branches; a third device for developing address modification signals as a function of said sets of condition signals and said microbranch code; and a fourth device for introducing said modification signals into said present microaddress at bit position designated by said microbranch code to form a new microaddress constituting the next microaddress for reading the next microinstruction.

Claim 11

The device defined in claim 5 wherein said condition bits are used to define the following codes: xb Ib Ab 0 0 0 Test for execution 0 0 1 Read c(A) 0 1 1 Read c(c(A)) 1 0 1 Read c(A+X) 1 1 1 Read c(c(A)+X).

Claim 12

In a system wherein instructions are read from a main memory and interpreted, under the control of logic, through the use of at least one ROM the output of the from providing logical control signals used in said logic to specify certain Mu -OPs relating to the use of said main memory as well as working registers and control memory, the system further providing for the receipt of branch, external, and data dependent condition signals, a branch Mu -OP control comprising: first logic means for setting up an initial ROM address as a function of the main instruction read from said main memory; second logic means for updating said ROM address during the sequencing of said ROM for nonbranching Mu -OPs; third logic means for detecting the presence of special branch Mu -OPS within the contents of the output of said ROM fourth logic means selectively controlled by said third logic means for developing modified ROM address signals as the combined function of said special Mu -OPs and said condition signals; and fifth logic means for introducing said modified address signals into the next address for said ROM.

Claim 13

In a system wherein instructions are read from a main memory and interpreted, under the control of logic, through the use of at least one ROM the output of the from providing logical control signals used in said logic to specify certain Mu -OPs relating to the use of said main memory as well as working registers and control memory, the system further providing for the receipt of branch, external, and data dependent condition signals, a branch Mu -OP control comprising: first logic means for setting up an initial ROM address as a function of the main instruction read from said main memory; second logic means for updating said ROM address during the sequencing of said ROM for nonbranching Mu -OPs; third logic means for detecting the presence of special branch Mu -OPS within the contents of the output of said ROM fourth logic means selectively controlled by said third logic means for developing modified ROM address signals as the combined function of said special Mu -OPs and said condition signals; and fifth logic means for introducing said modified address signals into the next address for said ROM.

Claim 14

The branch Mu -OP control defined in claim 7 wherein the branch conditions relate to indirect addressing, void address, and indexing.

Claim 15

The branch Mu -OP control defined in claim 7 wherein the branch conditions relate to arithmetic switching as a function of data conditions.

Claim 16

The branch Mu -OP control defined in claim 7 wherein separate ROM''s are provided for arithmetic control and address control, the arithmetic control ROM being an AU-ROM and the address control being AG-ROM.

Claim 17

The branch Mu -OP defined in claim 10 wherein said second logic means is used for arithmetic AU-ROM address nonbranch updating and derives the update address from a corresponding address field within the contents of the AU-ROM presently read.

Claim 18

The branch Mu -OP defined in claim 10 wherein said second logic means is used for address AG-ROM address nonbranch logic means and derives the update address as an incrementing function upon the present AG-ROM address.

Claim 19

A branching control comprising: first means for selecting condition signals related to a particular set of program branches; second means for logically identifying bit positions within a present instruction address register which relate to the possible entry points in a program following the execution of the program branches; and third means for generating address modification bits having respective logical associations with said condition signals and for introducing said modification bits into said logically identified bit positions within the present instruction address register.

Claim 20

A branching control comprising: first means for selecting condition signals related to a particular set of program branches; second means for logically identifying bit positions within a present instruction address register which relate to the possible entry points in a program following the execution of the program branches; and third means for generating address modification bits having respective logical associations with said condition signals and for introducing said modification bits into said logically identified bit positions within the present instruction address register.

Claim 21

In combination with a ROM, a ROM AG Address register, and a ROM Local register, a method of branching permitting 2n-way jumps in a store of microinstructions, where ''''n'''' is the number of branch conditions, said method comprising: specifying particular sets of condition bits in a microinstruction which apply to a branch operation; specifying particular bit positions in the present microinstruction location address where bit modifications are to be made to bits stored therein; developing modifying address bits having bit-to-bit correspondence with said condition bits; introducing said modifying address bits into said particular bit positions to form a modified branch address; and branching to said modified address of said store of microinstructions.

Claim 22

In combination with a ROM, a ROM AG Address register, and a ROM Local register, a method of branching permitting 2n-way jumps in a store of microinstructions, where ''''n'''' is the number of branch conditions, said method comprising: specifying particular sets of condition bits in a microinstruction which apply to a branch operation; specifying particular bit positions in the present microinstruction location address where bit modifications are to be made to bits stored therein; developing modifying address bits having bit-to-bit correspondence with said condition bits; introducing said modifying address bits into said particular bit positions to form a modified branch address; and branching to said modified address of said store of microinstructions.