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US4485440A
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Central processor utilization monitor
Assignee: Nokia Bell Labs
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Filing: 1984-02-13
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Granted: 1984-11-27
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Expires: 2004-02-13
Abstract
Abstract Data relative to code instruction use of a central processor unit (CPU) is collected by accumulating counts of code instructions to be executed upon termination of a clock interrupt process over a predetermined interval. Information stored on occurrence of a clock interrupt pulse is evaluated to determine if the code instruction is one under evaluation. If the code instruction is one under evaluation, a count in an associated memory location is incremented. Upon termination of the predetermined interval, the data is read out in histogram form. The data in the histogram is relative to the virtual addresses of the code instructions and, therefore, directly useable by a programmer to evaluate the code use of the CPU without the need for costly and time consuming data unmapping.
Inventors
- 👤 Thomas G. Duff
- 👤 Chester S. Zaluk
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:11
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F11/34; G06F11/3409; G06F11/3419; G06F11/3423; G06F11/3447; G06F11/3466; G06F2201/00; G06F2201/815; G06F2201/865; G06F2201/88
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
258 words
In a computer system including a clock generator for generating clock interrupt pulses at a predetermined rate which invoke a clock interrupt process, a central processor unit, and a memory having a plurality of memory locations, wherein in the clock interrupt process, upon occurrence of each of the clock interrupt pulses, the central processor unit generates and stores in predetermined ones of the memory locations first and second code words relating to a corresponding program code instruction to be executed by the central processor unit upon termination of the interrupt process, the first code word including a plurality of bits identifying a module in the program that the corresponding code instruction is in, and the second code word including a plurality of bits representing a virtual address of the corresponding code instruction, a method to be executed by the central processor unit for monitoring program code instruction utilization of the central processor unit, comprising the steps of, determining from said stored first code word bits whether said corresponding code instruction is in a program module under evaluation, determining from said stored second code word virtual address bits a mode of use of the central processor unit by said corresponding code instruction which is in the program module under evaluation, identifying a memory location in said memory assigned to said corresponding code instruction by utilizing predetermined ones of said stored second code word virtual address bits, and incrementing a count of said corresponding code instruction mode of use of the central processor unit stored in said assigned memory location.
Claim 2
Dependent Claim
258 words
In a computer system including a clock generator for generating clock interrupt pulses at a predetermined rate which invoke a clock interrupt process, a central processor unit, and a memory having a plurality of memory locations, wherein in the clock interrupt process, upon occurrence of each of the clock interrupt pulses, the central processor unit generates and stores in predetermined ones of the memory locations first and second code words relating to a corresponding program code instruction to be executed by the central processor unit upon termination of the interrupt process, the first code word including a plurality of bits identifying a module in the program that the corresponding code instruction is in, and the second code word including a plurality of bits representing a virtual address of the corresponding code instruction, a method to be executed by the central processor unit for monitoring program code instruction utilization of the central processor unit, comprising the steps of, determining from said stored first code word bits whether said corresponding code instruction is in a program module under evaluation, determining from said stored second code word virtual address bits a mode of use of the central processor unit by said corresponding code instruction which is in the program module under evaluation, identifying a memory location in said memory assigned to said corresponding code instruction by utilizing predetermined ones of said stored second code word virtual address bits, and incrementing a count of said corresponding code instruction mode of use of the central processor unit stored in said assigned memory location.
Claim 3
Dependent Claim
36 words
The method of claim 1 further including a step of incrementing a count in one of said memory locations of said corresponding code instruction which is determined not to be in said program module under evaluation.
Claim 4
Dependent Claim
40 words
The method of claim 2 wherein counts of said corresponding code instruction use of the central processor unit are accumulated during a predetermined interval, and further including a step of generating at least one graphical representation of said accumulated counts.
Claim 5
Dependent Claim
43 words
The method of claim 2 wherein counts of said corresponding code instruction use of the central processor unit are accumulated during a predetermined interval, and further including a step of generating at least one graphical representation of predetermined ones of said accumulated counts.
Claim 6
Dependent Claim
40 words
The method of claim 1 wherein the step of determining said mode of use of the central processor unit includes determining whether said mode of use is a first prescribed mode of use or a second prescribed mode of use.
Claim 7
Dependent Claim
101 words
The method of claim 5 wherein said second prescribed mode of use includes a plurality of types of use within said second mode, and if said corresponding code instruction is in said prescribed second mode of use, further including the step of determining from said stored second code word virtual address bits the type of use within said second mode, and wherein said step of incrementing further includes incrementing a count in a memory location assigned to said type of use and incrementing a count in a memory location assigned to accumulate a total count of said second mode of use.
Claim 8
Dependent Claim
71 words
The method of claim 5, if said corresponding code instruction is in said first prescribed mode of use, further including the steps of determining whether the mode of use of the central processor unit is idle by utilizing predetermined ones of said stored second code word virtual address bits, and if the mode of use is idle, incrementing a count in a memory location assigned to said idle mode of use.
Claim 9
Dependent Claim
118 words
The method of claim 7 wherein said first prescribed mode of use includes a plurality of priorities of use and predetermined bits of said stored first code word identify the priority of said first mode use, and if said corresponding code instruction is in said first prescribed mode of use and it is determined that said mode of use is not idle, further including the steps of determining a priority of use in said first mode by utilizing said stored first code word bits, incrementing a count in a memory location assigned to said priority of first mode use, and incrementing a count in a memory location assigned to accumulate a total count of the first mode use.
Claim 10
Dependent Claim
100 words
The method of claim 8 wherein said second prescribed mode of use includes a plurality of types of use within said mode, and if said corresponding code instruction is in said prescribed second mode of use, further including the step of determining from said stored second code word virtual address bits the type of use within said second mode, and wherein said step of incrementing further includes incrementing a count in a memory location assigned to said type of use and incrementing a count in a memory location assigned to accumulate a total count of said second mode of use.
Claim 11
Dependent Claim
36 words
The method of claim 9 further including a step of incrementing a count in one of said memory locations of said corresponding code instruction which is determined not to be in said program module under evaluation.
Claim 12
Dependent Claim
40 words
The method of claim 10 wherein counts of said corresponding code instruction use of the central processor unit are accumulated during a predetermined interval, and further including a step of generating at least one graphical representation of said accumulated counts.
Claim 13
Dependent Claim
43 words
The method of claim 10 wherein counts of said corresponding code instruction use of the central processor unit are accumulated during a predetermined interval, and further including a step of generating at least one graphical representation of predetermined ones of said accumulated counts.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-11-27 | 1988-05-28 | 1988-11-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-11-27 | 1992-05-28 | 1992-11-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-11-27 | 1996-05-28 | 1996-11-27 | $7700.00 | Window Closed / Lapsed |