US3893084A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory access control system
Assignee: Digital Equipment Corp
•
Filing: 1973-05-01
•
Granted: 1975-07-01
•
Expires: 1993-05-01
Abstract
Abstract A memory control for use in a digital computer system. During each memory reference certain use characteristics of the addressed location are monitored. These include the general accessibility of the location for any purpose, the availability of the location to certain users and operating restrictions which can be performed with information which the location contains. The control also monitors operational mode characteristics which indicate a class of operating programs being processed, whether the location contains an instruction or is for an operand and whether, in the case of an operand, a reading or writing operation is going to occur. If all the use and operational mode signals are comparable, the memory reference is allowed to continue. Otherwise it is aborted.
Inventors
- 👤 Alan Kotok
- 👤 Allan R Kent
- 👤 David A Gross
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:17
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/14; G06F12/1458
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
224 words
In a data processing system including a memory unit for storing information as instructions or data in storage locations with a unique address designating each storage location and a processor unit for processing in succession instructions in the memory unit, said processor unit including means for defining a plurality of operating modes, a generator for transmitting an address to identify one of the memory locations and to initiate a memory reference, and use signal means responsive to the address generator for transmitting signals corresponding to predetermined use characteristics of the addressed location, the improvement of circuitry for checking each memory reference, said circuitry including: A. a memory subroutine circuit in the processor unit for controlling information transfers between the processor unit and an addressed location, and B. a testing circuit comprising i. means activated upon the initiation of each memory reference for generating operating mode signals corresponding to the processor unit operating mode prevailing at that time, and ii. a validating circuit responsive to the use signal means and operating mode signal means during each memory reference and including means for enabling said memory subroutine circuit to effect a transfer when the signals corresponding to the use characteristic and prevailing operating mode indicate that the use characteristic and operating mode are compatible and means for disabling said memory subroutine circuit when they are incompatible.
Claim 2
Dependent Claim
224 words
In a data processing system including a memory unit for storing information as instructions or data in storage locations with a unique address designating each storage location and a processor unit for processing in succession instructions in the memory unit, said processor unit including means for defining a plurality of operating modes, a generator for transmitting an address to identify one of the memory locations and to initiate a memory reference, and use signal means responsive to the address generator for transmitting signals corresponding to predetermined use characteristics of the addressed location, the improvement of circuitry for checking each memory reference, said circuitry including: A. a memory subroutine circuit in the processor unit for controlling information transfers between the processor unit and an addressed location, and B. a testing circuit comprising i. means activated upon the initiation of each memory reference for generating operating mode signals corresponding to the processor unit operating mode prevailing at that time, and ii. a validating circuit responsive to the use signal means and operating mode signal means during each memory reference and including means for enabling said memory subroutine circuit to effect a transfer when the signals corresponding to the use characteristic and prevailing operating mode indicate that the use characteristic and operating mode are compatible and means for disabling said memory subroutine circuit when they are incompatible.
Claim 3
Dependent Claim
109 words
A data processing system as recited in claim 1 wherein an instruction memory reference retrieves an instruction from the memory unit and wherein the use signal means transmits a first use characteristic signal during a memory reference to a first set of memory locations haviNg a first restriction on the use thereof, said validating circuit including: i. instruction monitoring means for monitoring the first use charactertistic signals corresponding to each of the successive instructions, and ii. first comparing means connected to said instruction monitoring means and responsive to the first use characteristic signals corresponding to each of the successive instructions for energizing said disabling means in said validating circuit.
Claim 4
Dependent Claim
151 words
A system as recited in claim 2 wherein said processor unit includes an instruction decoder and wherein: A. said instruction monitoring means includes: i. first bistable means conditioned to a first state by the first use characteristic signal corresponding to a current instruction in the processor unit, and ii. second bistable means conditioned to a first state by the first use characteristic signal corresponding to a preceding instruction which was in the processor unit, and B. said first comparing means includes: i. means connected to said first and second bistable means for generating an error signal when said first bistable means is in its first state and said second bistable means is in its second state, said validating circuit disabling means being responsive to the error signal, and ii. means coupled to the instruction decoder for disabling said error signal generating means in response to the processing of a preselected instruction.
Claim 5
Dependent Claim
73 words
A system as recited in claim 2 wherein an operand memory reference transfers data between the memory unit and processor unit, said validating circuit additionally comprising: A. operand monitoring means for monitoring other use characteristic signals during operand memory references, and B. second comparing means connected to said operand monitoring means and responsive to the other use of characteristic signals and operating mode signals for energizing said disabling means in said validating circuit.
Claim 6
Dependent Claim
48 words
A system as recited in claim 4 wherein the memory unit stores a plurality of programs each comprising a plurality of instructions, said second comparing means including means connected to said instruction monitoring means and said operand monitoring means for energizing said disabling means in said validating circuit.
Claim 7
Dependent Claim
83 words
A system as recited in claim 4 wherein A. said use signal means includes means for transmitting a second use characteristic signal when data can be transferred to the corresponding location, B. said operating mode signal generating a WRITING signal when an operand memory reference is to transfer data to a location, and C. said second comparing means including means responsive to the WRITING signal and the absence of the second use characteristic signal for energizing said disabling means in said validating circuit.
Claim 8
Dependent Claim
70 words
A system as recited in claim 4 wherein said memory unit stores instructions grouped as programs, at least one program being designated a control program, A. said use signal means includes means for transmitting a third use characteristic signal when an addressed location contains a control program, B. said processor unit operating mode signal generating means including means for transmitting a CONTROL PROGRAM operating mode signal when processing control programs.
Claim 9
Dependent Claim
65 words
A system as recited in claim 7 wherein: A. said operating mode signal generating means includes means for transmitting a WRITING signal when an operand memory reference is to transfer data to a memory location, and B. said second comparing means includes means responsive to the WRITING signal and the first and third use characteristic signals for energizing said disabling means in said validating circuit.
Claim 10
Dependent Claim
45 words
A system as recited in claim 7 wherein said second comparing means includes a means responsive to the first use characteristic signal and the absence of the third use characteristic signal during an operand memory referencE for energizing said disabling means in said validating circuit.
Claim 11
Dependent Claim
124 words
A system as recited in claim 1 wherein the memory locations are grouped in executive and user pages and an address defines a page and location on the page, wherein the address generator includes paging means for storing paging information including the use characteristics of that page and wherein said use signal means is connected to said paging means for transmitting a first use characteristic signal when the availability of the page is restricted, said validating circuit comprising: i. instruction monitoring means for monitoring the first use characteristic signal corresponding to each of the successive instructions, and ii. first comparing means responsive to the first use characteristic signals corresponding to each of the successive instructions for energizing said disabling means in said validating circuit.
Claim 12
Dependent Claim
92 words
A system as recited in claim 10 wherein an operand memory reference transfers data between the memory unit and processor unit, said use signal means transmitting a second use characteristric signal when a different restriction exists for the use of the information on the page, said validating circuit additionally comprising: i. operand monitoring means for monitoring the use characteristic signals during operand memory references, and ii. second comparing means responsive to the use characteristic and operating mode signals during an operand memory reference for energizing said disabling means in said validating circuit.
Claim 13
Dependent Claim
102 words
A system as recited in claim 10 wherein said paging means stores only a portion of the paging information, the memory unit having locations for storing all paging information and wherein the address generator includes refill means for transferring new paging information into the paging means, said validating circuit additionally comprising: i. means monitoring the refilll means and paging means for generating an error signal if, after a paging information transfer, the paging means does not contain appropriate paging information, and ii. means responsive to the error signal from said refill monitoring means for energizing said disabling means in said validating circuit.
Claim 14
Dependent Claim
67 words
A system as recited in claim 12 wherein an operand memory reference transfers data between the memory unit and processor unit and said validating circuit additionally comprises: i. operand monitoring means for monitoring the use characteristic signals during operand memory references, and ii. third comparing means including means for energizing said enabling means in said validating circuit in response to comparable use characteristic and operating mode signals.
Claim 15
Dependent Claim
82 words
A system as recited in claim 13 wherein the memory locations are grouped in pages, certain programs being designated control programs, at least one control program including unpaged instructions which produce specific addresses, A. said operating mode signal generating means generating an unpaged operating mode signal during the processing of unpaged instructions, and B. said third comparing means including means responsive to the first use characteristic signal and the unpaged operating mode signal for energizing said enabling means in said validating circuit.
Claim 16
Dependent Claim
98 words
A system as recited in claim 13 wherein the use signal means includes means for transmitting a second use characteristic when data can be transferred to that memory location, A. said operating mode generating means including means for generating a WRITING signal during a memory reference for transferring data to a memory location, B. said third means including means responsive to the first value of the second use characteristic signal during an operand memory reference and the absence of the first use characteristic signal from said instruction monitoring means for energizing said enabling means in said validating circuit.
Claim 17
Dependent Claim
115 words
A system as recited in claim 13 wherein the memory Locations are grouped in pages, each page storing at least one program and at least one program being designated a control program, and at least one program being located on a page which causes the use signal means to transmit the the first use characteristic signal, A. said operating mode generating means including means for generating a signal during an operand memory reference when data is to be transferred fron a memory location, B. said third comparing means including means responsive to the first use characteristic signal during an operand memory reference and the READING signal for energizing the enabling means in said validating circuit.
References Cited (Backward Citations)
US3555515A
Cited
US3328768A
Cited
US3377619A
Cited
US3377624A
Cited
US3576544A
Cited
US3609697A
Cited
US3599159A
Cited
US3771146A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-06-30 | 1978-12-30 | 1979-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-06-30 | 1982-12-30 | 1983-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-06-30 | 1986-12-30 | 1987-07-01 | $7700.00 | Window Closed / Lapsed |