Patent US4402055A successfully refreshed from Google Patents.
US4402055A
Expired / Lapsed
US
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Automatic test system utilizing interchangeable test devices
Assignee: Westinghouse Electric Corp
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Filing: 1981-01-27
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Granted: 1983-08-30
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Expires: 2001-01-27
Abstract
Abstract An automatic test system controlled by a general purpose digital central processor is disclosed. The central processor accepts test programs in a high level compiler language such as Atlas. The Atlas program is compacted into a simplified language which is utilized to communicate with test devices via a standard IEEE 488 data bus. Each of the test devices includes a programmable interface digital processor which performs any translation that may be necessary in order to permit specific test instruments coupled to the central processor via the interface processor to perform the tests specified by the high level test programs. A switching matrix also communicates with the digital processor to connect the appropriate test device to the unit under test.
Inventors
- 👤 Raymond A. Lloyd
- 👤 Larry L. Charles
- 👤 William F. Susie
- 👤 Allen W. Tate, Jr.
- 👤 James R. Reeder
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 11:17
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31907; G01R31/2832; G01R31/2834; G01R31/3183; G01R31/318342; G01R31/31912; G01R31/31917; G01R31/31926; G06; G06F; G06F2201/00; G06F2201/865
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
234 words
A test system, comprising in combination: a. a central programmable digital processor for accepting a test program in a first high level compiler language, said program comprising a plurality of program sequences each specifying a test to be performed on a unit under test; b. a plurality of test devices each including a programmable processor and at least one test instrument coupled to communicate with said programmable digital processor via a data bus using a compacted (i.e. simplified version) of said high-level compiler language; c. a switch matrix coupled to receive switching commands from said programmable digital processor via a data bus and the data input/output line from said test devices; wherein d. each sequence of said program in said first high level compiler language specifying a test to be performed is compacted by said programmable digital processor to produce program sequences in said compact version of said first high level compiler language with portions of said program sequences in said compact version of said high level compiler language relating to one of said test instrument being coupled to said programmable processor comprising a portion of at least one of said plurality of test devices which in response thereto generates the signals required by said at least one test instrument to perform the specified test and to said switch matrix to couple said at least one test instrument to said apparatus to be tested.
Claim 2
Dependent Claim
234 words
A test system, comprising in combination: a. a central programmable digital processor for accepting a test program in a first high level compiler language, said program comprising a plurality of program sequences each specifying a test to be performed on a unit under test; b. a plurality of test devices each including a programmable processor and at least one test instrument coupled to communicate with said programmable digital processor via a data bus using a compacted (i.e. simplified version) of said high-level compiler language; c. a switch matrix coupled to receive switching commands from said programmable digital processor via a data bus and the data input/output line from said test devices; wherein d. each sequence of said program in said first high level compiler language specifying a test to be performed is compacted by said programmable digital processor to produce program sequences in said compact version of said first high level compiler language with portions of said program sequences in said compact version of said high level compiler language relating to one of said test instrument being coupled to said programmable processor comprising a portion of at least one of said plurality of test devices which in response thereto generates the signals required by said at least one test instrument to perform the specified test and to said switch matrix to couple said at least one test instrument to said apparatus to be tested.
Claim 3
Dependent Claim
19 words
A test system in accordance with claim 1 wherein each of said test devices includes a programmable digital processor.
Claim 4
Dependent Claim
59 words
A test system in accordance with claim 2 wherein each of said programmable digital processors are coupled to said central processor to selectively receive instructions from said central processor and in response thereto control a specific test instrument causing said specific test instrument to perform test specified thereby and couple the results of said test to said central processor.
Claim 5
Dependent Claim
39 words
A test system in accordance with claim 3 wherein said switching matrix includes a programmable digital processor for receiving instructions from said central processor and in response thereto coupling one of said test devices to apparatus to be tested.
Claim 6
Dependent Claim
92 words
A test device for use in an automatic test system, said test system being controlled by a central programmed digital processor utilizing program sequences in a high level compiler language; said test device comprising: a. a first interface unit for coupling to the data bus of said central programmed processor; b. a programmable digital processor coupled to communicate with said central programmable digital processor via said first interface unit; c. a digitally controlled test instrument; and d. a second interface unit coupling said programmable digital processor to said digitally controlled test instrument.
Claim 7
Dependent Claim
92 words
A test device for use in an automatic test system, said test system being controlled by a central programmed digital processor utilizing program sequences in a high level compiler language; said test device comprising: a. a first interface unit for coupling to the data bus of said central programmed processor; b. a programmable digital processor coupled to communicate with said central programmable digital processor via said first interface unit; c. a digitally controlled test instrument; and d. a second interface unit coupling said programmable digital processor to said digitally controlled test instrument.
Claim 8
Dependent Claim
20 words
A test device in accordance with claim 5 wherein said interface processor includes a read only memory for storing programs.
Claim 9
Dependent Claim
20 words
A test device in accordance with claim 6 wherein said programmable digital processor includes a read/write memory for data processing.
Claim 10
Dependent Claim
18 words
A test system in accordance with claim 7 wherein said read only memory is a random access memory.
Claim 11
Dependent Claim
17 words
A test device in accordance with claim 8 wherein said read/write memory is a random access memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-08-29 | 1987-02-28 | 1987-08-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-08-29 | 1991-02-28 | 1991-08-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-08-29 | 1995-02-28 | 1995-08-30 | $7700.00 | Window Closed / Lapsed |