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US3694632A Expired / Lapsed US ⏱️ 0.0 years remaining

Automatic test equipment utilizing a matrix of digital differential analyzer integrators to generate interrogation signals

Assignee: Hawker Siddeley Dynamics Ltd
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Filing: 1970-12-28
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Granted: 1972-09-26
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Expires: 1990-12-28
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Abstract

Abstract In computer-controlled automatic test or check-out equipment, interrogation signals for application to a unit under test are generated by a matrix of digital differential analyzer integrators, the digital outputs of the matrix be applied to digital-to-analogue converters so as to produce analogue signals to be fed to the unit under test. The computer provides initial control signals to determine the connections within the matrix and to set in initial values in the registers of the integrators, after which the matrix is driven by its own clock pulse generator, leaving the computer free for processing the response signals from the unit under test.

Inventors

  • 👤 David John Bloomer

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-22 18:28
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/02; G06F1/022; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31926; G06F7/00; G06F7/60; G06F7/64

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 178 words
Computer-controlled automatic test equipment, comprising a digital computer for controlling the testing and also for analyzing returning signal responses resulting from the testing at least one peripheral input device supplying information to said computer, at least one peripheral output device receiving information from said computer, a plurality of analogue-todigital converters, a routing system for routing analogue signals to a unit under test and also for routing analogue signal responses from the unit under test to said analogue-to-digital converters, a response input channel of said computer receiving for computer analysis the digital signal outputs of said analogue-to-digital converters, a plurality of digital differential analyzer integrators combined into a matrix with variable interconnections for synthesizing a variety of digital test signals, a control output channel of said computer delivering computer output signals to said matrix to determine said matrix interconnections and also to set the initial conditions in said integrators, and a plurality of digital-toanalogue converters receiving said synthesized digital test signals from said matrix and converting them into said analogue test signals which are delivered to said routing system.
Claim 2
Dependent Claim 178 words
Computer-controlled automatic test equipment, comprising a digital computer for controlling the testing and also for analyzing returning signal responses resulting from the testing at least one peripheral input device supplying information to said computer, at least one peripheral output device receiving information from said computer, a plurality of analogue-todigital converters, a routing system for routing analogue signals to a unit under test and also for routing analogue signal responses from the unit under test to said analogue-to-digital converters, a response input channel of said computer receiving for computer analysis the digital signal outputs of said analogue-to-digital converters, a plurality of digital differential analyzer integrators combined into a matrix with variable interconnections for synthesizing a variety of digital test signals, a control output channel of said computer delivering computer output signals to said matrix to determine said matrix interconnections and also to set the initial conditions in said integrators, and a plurality of digital-toanalogue converters receiving said synthesized digital test signals from said matrix and converting them into said analogue test signals which are delivered to said routing system.
Claim 3
Dependent Claim 45 words
Equipment according to claim 1, wherein a clock pulse generator is provided to drive the integrator matrix after the interconnections and initial conditions have been determined by the computer signals, thereby leaving the computer free to process response signalS returning from the unit under test.

References Cited (Backward Citations)

US3601591A Cited
US3598974A Cited
US3487304A Cited
US3586837A Cited
US3585500A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-09-26 1976-03-27 1976-09-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-09-26 1980-03-27 1980-09-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-09-26 1984-03-27 1984-09-26 $7700.00 Window Closed / Lapsed

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