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US4393498A
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Method and apparatus for testing systems that communicate over digital buses by transmitting and receiving signals in the form of standardized multi-bit binary encoded words
Assignee: Boeing Co
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Filing: 1981-01-22
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Granted: 1983-07-12
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Expires: 2001-01-22
Abstract
Abstract An apparatus is disclosed for testing line replaceable units (LRUs) of an avionics system in which the various units of the system exchange information by means of transmitting and/or receiving digital communication words, each word having a predetermined, standardized format. In a transmit test mode of the apparatus, the information content of a test word is formulated in either engineering or binary form by using a keyboard to create the word manually, or by retrieving a preprogrammed word or sequence of dynamically changing words from a plug-in programmable read only memory (PROM). Once formulated and stored, the communication word is repetitively transmitted, at selected word and bit transfer rates, from one or more output ports provided on the test set and applied, by a jumper connection, to a data communication bus that, in turn, is connected to one or more avionic LRUs. A CRT on the control panel of the test set simultaneously displays the information content of the transmit word, both in engineering and binary form. In a receive mode, a signal receiving port is coupled to a communication bus associated with one or more avionics LRUs for monitoring preselected communication words that are exchanged between the LRUs connected to that bus. The received word or words are decoded by the test set and displayed both in engineering and binary form on the CRT. The transmit and receive modes may be used concurrently so that a given LRU or groups of LRUs can be stimulated by one or more transmit words, and the word responses of such LRUs monitored. In a further mode, called receive-all, an abbreviated form (LABEL) of the engineering notation of each word present on a monitored data bus is displayed on the CRT, allowing the user to select certain words from among the displayed LABELs for full-word processing in the above-mentioned receive mode.
Inventors
- 👤 Tee-Squant-Nee Jackson
- 👤 Paul M. Vernon
- 👤 David A. Schoen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 19:23
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/273; G06F11/277
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
299 words
A test apparatus for testing systems that communicate by transmission and/or reception of transmit and/or receive words, respectively, in which such words are organized in a predetermined multiple bit format, comprising: computer means including a memory; data entry means for entering into the memory of said computer means the content of a first multi-bit transmit word in either engineering notation or in binary encoded notation; said computer means further including engineering to binary conversion processing means for accepting and converting the content of a transmit word in said memory when entered in said engineering notation, into said binary encoded notation; a first transmit port; transmit circuit means responsive to said computer means for formatting and transmitting said first transmit word in binary notation from said first transmit port; receiving circuit means for receiving a multiple bit receive word in binary notation, said receiving circuit means including means responsive to said computer means for receiving and storing said receive word in binary notation in said memory of said computer means; said computer means further having binary to engineering conversion processing means for converting the context of said first transmit word to engineering notation when entered into said memory in binary notation, and for converting the receive word, as received in binary notation, to engineering notation; a display device responsive to display control signals for displaying alphanumeric symbols; and, said computer means including a first display control processing means for generating display control signals that cause said display device to concurrently display the contents of the first transmit word both in engineering and binary notations, and said computer means including a second display control processing means for generating display control signals that cause said display device to concurrently display the contents of the received word both in binary and engineering notations.
Claim 2
Dependent Claim
299 words
A test apparatus for testing systems that communicate by transmission and/or reception of transmit and/or receive words, respectively, in which such words are organized in a predetermined multiple bit format, comprising: computer means including a memory; data entry means for entering into the memory of said computer means the content of a first multi-bit transmit word in either engineering notation or in binary encoded notation; said computer means further including engineering to binary conversion processing means for accepting and converting the content of a transmit word in said memory when entered in said engineering notation, into said binary encoded notation; a first transmit port; transmit circuit means responsive to said computer means for formatting and transmitting said first transmit word in binary notation from said first transmit port; receiving circuit means for receiving a multiple bit receive word in binary notation, said receiving circuit means including means responsive to said computer means for receiving and storing said receive word in binary notation in said memory of said computer means; said computer means further having binary to engineering conversion processing means for converting the context of said first transmit word to engineering notation when entered into said memory in binary notation, and for converting the receive word, as received in binary notation, to engineering notation; a display device responsive to display control signals for displaying alphanumeric symbols; and, said computer means including a first display control processing means for generating display control signals that cause said display device to concurrently display the contents of the first transmit word both in engineering and binary notations, and said computer means including a second display control processing means for generating display control signals that cause said display device to concurrently display the contents of the received word both in binary and engineering notations.
Claim 3
Dependent Claim
85 words
The test apparatus of claim 1, wherein said predetermined format of said notation of the receive word includes a first field of bits representing a label identifying the nature of the word, and at least one other field of bits representing engineering data, and wherein said receiving circuit means comprises means responsive to entry by said data entry means of said label for a selected receive word to receive and store in said memory of said computer only that receive word having said selected label.
Claim 4
Dependent Claim
125 words
The test apparatus of claim 1, wherein the predetermined format of the multi-bit word in binary notation includes a first field of bits representing a label identifying such word, and at least another field of bits representing engineering data, and wherein said computer means further comprises: a receive-all processing means responsive to said receiving circuit means for receiving a plurality of multi-bit receive words and storing in said memory and first fields of bit representing the labels of such words; label conversion processing means for converting said first field of bits of each receive word into engineering notation; and, third display control processing means for generating display control signals that cause said display device to concurrently display the labels of said plurality of receive words.
Claim 5
Dependent Claim
46 words
The test apparatus of claim 1, wherein said transmit circuit means comprises means for successively transmitting said first transmit word automatically in succession a preselected number of times, so as to cause a burst of transmit words of the same content to be generated and transmitted.
Claim 6
Dependent Claim
66 words
The test apparatus of claim 1, wherein said data entry means includes means for entering into the memory of said computer means the content of a second multi-bit transmit word in either decoded engineering notation or in binary encoded notation; and, a second transmit port, said transmit circuit means being responsive to said computer means to transmit said second transmit word from said second transmit port.
Claim 7
Dependent Claim
27 words
The test apparatus of claim 5, wherein said computer means and said transmit circuit means include means for concurrent transmission of said first and second transmit words.
Claim 8
Dependent Claim
39 words
The test apparatus of claim 6, wherein said computer means and said transmit circuit means further comprise: transmission rate selection and control means for selectively and independently setting the rates of transmission of said first and second transmit words.
Claim 9
Dependent Claim
32 words
The test apparatus of claim 7, wherein said transmission rate selection and control means comprise means for setting the bit speed of transmission and means for setting the word rate of transmission.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-07-11 | 1987-01-10 | 1987-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-07-11 | 1991-01-10 | 1991-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-07-11 | 1995-01-10 | 1995-07-12 | $7700.00 | Window Closed / Lapsed |