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US3920973A Expired / Lapsed US ⏱️ 0.0 years remaining

Method and system for testing signal transmission paths

Assignee: Westinghouse Electric Corp
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Filing: 1973-01-09
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Granted: 1975-11-18
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Expires: 1993-01-09
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Abstract

Abstract The disclosure relates to a method and system for testing a plurality of paths over which discrete d.c. signal levels are transmitted between a digital computer and external equipment. A particular configuration of discrete d.c. signal levels is applied to the input or output paths and a signal generated which is related to the sum of the d.c. signal levels on the paths to be tested. A test circuit in a computer input/output unit generates a reference signal and the sum signal may then be evaluated. An unfavorable evaluation may activate a fault indicator.

Inventors

  • 👤 Karl B Avellar
  • 👤 James E Buchanan

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-22 20:15
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/221; G01; G01R; G01R31/00; G01R31/28; G01R31/30; G01R31/3004; G06F11/2221; H; H04; H04L; H04L1/00; H04L1/24

Claims Analysis

Total Claims: 16
Claim 1
Independent Claim 106 words
A system for testing a plurality of paths over which discrete d.c. signal levels are transmitted between a digital computer and external equipment comprising: external means for transmitting a configuration of said discrete d.c. signal levels over said plurality of paths; a computer input/output unit remote from said transmitting means and including means for generating a sum signal related to the sum of the discrete d.c. signal levels transmitter over said plurality of paths; a digital computer including means for causing the evaluation of said sum signal with respect to the transmitted configuration of discrete d.c. signal levels and for manifesting the results of the evaluation.
Claim 2
Independent Claim 106 words
A system for testing a plurality of paths over which discrete d.c. signal levels are transmitted between a digital computer and external equipment comprising: external means for transmitting a configuration of said discrete d.c. signal levels over said plurality of paths; a computer input/output unit remote from said transmitting means and including means for generating a sum signal related to the sum of the discrete d.c. signal levels transmitter over said plurality of paths; a digital computer including means for causing the evaluation of said sum signal with respect to the transmitted configuration of discrete d.c. signal levels and for manifesting the results of the evaluation.
Claim 3
Dependent Claim 34 words
The system of claim 1 wherein sum signal generating means comprises a summing amplifier for generating an analog sum signal related in levels to the sum of the amplitudes of the discrete signal levels.
Claim 4
Dependent Claim 33 words
The system of claim 2 wherein said summing amplifier includes means for modifying the sum signal by a predetermined amount to compensate for undesired variations in the levels of said discrete signal levels.
Claim 5
Dependent Claim 42 words
The system of claim 1 wherein said evaluation causing means performs the functions of: detecting the configuration of discrete d.c. signal levels transmitted over said paths; and, comparing said sum signal to a reference signal selected in response to the detected configuration.
Claim 6
Dependent Claim 42 words
The system of claim 3 wherein said evaluation causing means performs the functions of: detecting the configuration of discrete d.c signal levels transmitted over said paths; and, comparing said sum signal to a reference signal selected in response to the detected configuration.
Claim 7
Independent Claim 169 words
A system for testing a plurality of paths for transmission of discrete d.c. signal levels comprising: means for transmitting a configuration of discrete d.c. signal levels over said plurality of paths; means responsive to and remote from said transmitting means for generating a digital signal representative of the sum of the amplitudes of the discrete signal levels transmitted over said plurality of paths; means for storing a plurality of digital signals each representative of the sum of the discrete signal levels for a predetermined configuration of discrete signal levels transmitted Over said paths; means for ascertaining the configuration of discrete signal levels being transmitted over said plurality of signal paths; means for selecting one of said plurality of stored digital signals in response to the ascertained configuration; means for comparing said generated digital signal with said selected one of said stored signals; and, means operatively connected to said comparing means for indicating a fault in one of said paths in response to an unfavorable comparison of said digital signals.
Claim 8
Independent Claim 169 words
A system for testing a plurality of paths for transmission of discrete d.c. signal levels comprising: means for transmitting a configuration of discrete d.c. signal levels over said plurality of paths; means responsive to and remote from said transmitting means for generating a digital signal representative of the sum of the amplitudes of the discrete signal levels transmitted over said plurality of paths; means for storing a plurality of digital signals each representative of the sum of the discrete signal levels for a predetermined configuration of discrete signal levels transmitted Over said paths; means for ascertaining the configuration of discrete signal levels being transmitted over said plurality of signal paths; means for selecting one of said plurality of stored digital signals in response to the ascertained configuration; means for comparing said generated digital signal with said selected one of said stored signals; and, means operatively connected to said comparing means for indicating a fault in one of said paths in response to an unfavorable comparison of said digital signals.
Claim 9
Dependent Claim 49 words
The system of claim 6 wherein said digital signal generating means comprises: a summing amplifier for generating an analog signal related in amplitude to the sum of the amplitudes of the discrete signal levels; and, an analog to digital converter for converting said analog signal into said digital signal.
Claim 10
Dependent Claim 32 words
The system of claim 7 wherein said summing amplifier includes means for modifying the sum signal by a predetermined amount to compensate for variations in the amplitude of said discrete signal levels.
Claim 11
Independent Claim 122 words
A method for testing an apparatus which includes a plurality of paths over which discrete d.c. signal levels are transmitted between a computer and external equipment through a computer input/output unit wherein the plurality of paths are tested by the apparatus automatically performing the steps of: a. transmitting a configuration of said discrete d.c. signal levels over said plurality of paths from a location remote from the input/output unit; b. generating, at the input/output unit, a sum signal related to the sum of the discrete d.c. signal levels transmitted over said plurality of paths; c. evaluating, at the digital computer, the sum signal with respect to the transmitted configuration of discrete d.c. signal levels; and, d. manifesting the results of the evaluation.
Claim 12
Independent Claim 122 words
A method for testing an apparatus which includes a plurality of paths over which discrete d.c. signal levels are transmitted between a computer and external equipment through a computer input/output unit wherein the plurality of paths are tested by the apparatus automatically performing the steps of: a. transmitting a configuration of said discrete d.c. signal levels over said plurality of paths from a location remote from the input/output unit; b. generating, at the input/output unit, a sum signal related to the sum of the discrete d.c. signal levels transmitted over said plurality of paths; c. evaluating, at the digital computer, the sum signal with respect to the transmitted configuration of discrete d.c. signal levels; and, d. manifesting the results of the evaluation.
Claim 13
Dependent Claim 42 words
The method of claim 9 wherein the sum signal is a digital signal and is generated by summing the amplitudes of the discrete signal levels to provide an analog sum signal and converting the analog sum signal into a digital sum signal.
Claim 14
Dependent Claim 30 words
The method of claim 10 including the step of modifying the sum signal by a predetermined amount to compensate for undesired variations in the amplitudes of said discrete signal levels.
Claim 15
Dependent Claim 53 words
The method of claim 11 wherein the evaluation of the sum signal is accomplished by the digital computer and includes the steps of: i. detecting the configuration of discrete d.c. signal levels transmitted over said paths; and, ii. comparing the sum signal to a reference signal selected in response to the detected configuration.
Claim 16
Dependent Claim 53 words
The method of claim 9 wherein the evaluation of the sum signal is accomplished by the digital computer and includes the steps of: i. detecting the configuration of discrete d.c. signal levels transmitted over said paths; and, ii. comparing the sum signal to a reference signal selected in response to the detected configuration.

References Cited (Backward Citations)

GB1179243A Cited
US3609312A Cited
US3591790A Cited
US3681758A Cited
US3710350A Cited
US3746850A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-11-17 1979-05-19 1979-11-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-11-17 1983-05-19 1983-11-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-11-17 1987-05-19 1987-11-18 $7700.00 Window Closed / Lapsed

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