Patent US4300152A successfully refreshed from Google Patents.
US4300152A
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Complementary field-effect transistor integrated circuit device
Assignee: AT&T Inc
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Filing: 1980-04-07
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Granted: 1981-11-10
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Expires: 2000-04-07
Abstract
Abstract A CMOS integrated circuit structure which is not susceptible to latchup utilizes insulated-gate field-effect transistors having Schottky barrier source and drains (SB-IGFET). In the preferred embodiment, the n-channel device of an adjacent complementary pair of transistors in a CMOS circuit is provided with diffused source and drain while the p-channel device of the pair is provided with PtSi-Si Schottky barrier contact source and drain. Such a structure completely eliminates the parasitic pnpn structure which causes the latchup problem in conventional CMOS structures.
Inventors
- 👤 Martin P. Lepselter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:42
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
156 words
A complementary field-effect transistor integrated circuit device comprising a semiconductive body having a first bulk region of one conductivity type extending from a surface of the body; a second bulk region, of a conductivity type which is opposite to the one type, extending from the surface; and a pair of complementary transistors adjacent the surface, one of the pair being of the opposite channel conductivity type and having spaced source and drain situated in the first bulk region, the other of the pair being of the one channel conductivity type and having spaced source and drain situated in the second bulk region; characterized in that the source and drain of at least one of the complementary pair of transistors each consists of a connection that is substantially incapable of injecting minority carriers when forward biased with respect to the bulk region in which the connection is situated whereby there are avoided the parasitic conditions for latchup.
Claim 2
Dependent Claim
156 words
A complementary field-effect transistor integrated circuit device comprising a semiconductive body having a first bulk region of one conductivity type extending from a surface of the body; a second bulk region, of a conductivity type which is opposite to the one type, extending from the surface; and a pair of complementary transistors adjacent the surface, one of the pair being of the opposite channel conductivity type and having spaced source and drain situated in the first bulk region, the other of the pair being of the one channel conductivity type and having spaced source and drain situated in the second bulk region; characterized in that the source and drain of at least one of the complementary pair of transistors each consists of a connection that is substantially incapable of injecting minority carriers when forward biased with respect to the bulk region in which the connection is situated whereby there are avoided the parasitic conditions for latchup.
Claim 3
Dependent Claim
26 words
An integrated circuit device of claim 1 further characterized in that the connection that is substantially incapable of injecting minority carriers is a Schottky barrier connection.
Claim 4
Dependent Claim
81 words
An integrated circuit device of claim 1 wherein the one conductivity type is n-type and the opposite conductivity type is p-type and further characterized in that the source and drain of the n-channel conductivity type transistor each comprise a relatively heavily doped n-type region formed in the second bulk region and further characterized in that the source and drain of the p-channel conductivity type transistor each consists of a Schottky barrier connection made to the surface of the first bulk region.
Claim 5
Dependent Claim
47 words
The integrated circuit device of claim 3 wherein the semiconductive body is silicon and further characterized in that Schottky barrier connections of the source and drain of the p-channel conductivity type transistor each comprise a PtSi layer in contact with the surface of the first bulk region.
References Cited (Backward Citations)
US3590471A
Cited
US3708360A
Cited
US4015147A
Cited
US4152717A
Cited
US4053925A
Cited
US4203126A
Cited
US4035826A
Cited
US4137545A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-11-09 | 1985-05-11 | 1985-11-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-11-09 | 1989-05-11 | 1989-11-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-11-09 | 1993-05-11 | 1993-11-10 | $7700.00 | Window Closed / Lapsed |