US4237534A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bus arbiter
Assignee: Motorola Solutions Inc
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Filing: 1978-11-13
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Granted: 1980-12-02
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Expires: 1998-11-13
Abstract
Abstract An improved multiprocessor bus arbiter which provides dynamically prioritized access for a plurality of processors to shared peripheral devices on a common bus through bus access switches. The arbiter includes logic circuitry to which incoming bus access request signals are coupled and a memory means which stores bus access status. The logic circuit determines bus access based on the input request signal and the stored information. The arbiter is adapted to provide a cycle shared mode of access or a lock out mode of access, as may be required.
Inventors
- 👤 Kenneth A. Felix
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 14:25
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/18; G06F13/36; G06F13/362; G06F13/364
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
246 words
A bus arbiter for providing, in response to bus access request signals from two or more controllers, dynamically prioritized access to a common bus of a digital system have at least one peripheral device coupled to the common bus, and said two or more controllers coupled to the common bus through respective bus access switching means, said switching means activated by applied present bus access grant signals, the arbiter comprising: (a) a plurality of logic circuits each having input means coupled to a plurality of decoding AND gates inputs and the outputs of the AND gates are coupled to an OR gate, for generating at the output of the OR gate a future bus access grant signal based on the bus access request signals and one or more present bus access grant signals applied to said input means; (b) a plurality of memory devices for storing the present bus access grant signal, each of said memory devices coupled to the output of each said OR gate for updating the present bus access grant signal of the memory devices in response to the future bus access grant signal, and each memory device having an output terminal for applying the present bus access grant signal to the bus access switching means; and (c) direct feedback means for coupling the output terminal of at least one of the memory means to the input memory devices of each logic circuit supply the present bus access grant signal information thereto .
Claim 2
Dependent Claim
246 words
A bus arbiter for providing, in response to bus access request signals from two or more controllers, dynamically prioritized access to a common bus of a digital system have at least one peripheral device coupled to the common bus, and said two or more controllers coupled to the common bus through respective bus access switching means, said switching means activated by applied present bus access grant signals, the arbiter comprising: (a) a plurality of logic circuits each having input means coupled to a plurality of decoding AND gates inputs and the outputs of the AND gates are coupled to an OR gate, for generating at the output of the OR gate a future bus access grant signal based on the bus access request signals and one or more present bus access grant signals applied to said input means; (b) a plurality of memory devices for storing the present bus access grant signal, each of said memory devices coupled to the output of each said OR gate for updating the present bus access grant signal of the memory devices in response to the future bus access grant signal, and each memory device having an output terminal for applying the present bus access grant signal to the bus access switching means; and (c) direct feedback means for coupling the output terminal of at least one of the memory means to the input memory devices of each logic circuit supply the present bus access grant signal information thereto .
Claim 3
Dependent Claim
76 words
The bus arbiter of claim 1, including a control logic circuit, coupled to the memory devices and having input means for input of the present bus access grant signal and bus access request signals, for maintaining a present access grant signal to a particular access switch and to lock out access grant signals to other switches whereby access to the common bus is maintained until the access request signal from the currently accessing controller is removed.
Claim 4
Dependent Claim
32 words
The bus arbiter of claims 1 or 2 or 5 wherein each said AND gate is replaced by a NAND gate and each said OR gate is replaced by a NOR gate.
Claim 5
Dependent Claim
15 words
The bus arbiter of claims 1 or 2 wherein each memory device comprises a latch.
Claim 6
Dependent Claim
34 words
The bus arbiter of claim 1 wherein said arbiter is adapted to operate in a cyclic mode in response to bus access request signals for providing access to the common bus in successive cycles.
References Cited (Backward Citations)
US3348210A
Cited
US3665487A
Cited
US3693161A
Cited
US3761879A
Cited
US3787818A
Cited
US3810114A
Cited
US3728693A
Cited
US3886524A
Cited
US4017841A
Cited
US4047157A
Cited
US3984819A
Cited
US4130865A
Cited
US3979730A
Cited
US4030079A
Cited
US4016546A
Cited
US4096572A
Cited
US4041472A
Cited
US4096571A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-12-02 | 1984-06-02 | 1984-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-12-02 | 1988-06-02 | 1988-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-12-02 | 1992-06-02 | 1992-12-02 | $7700.00 | Window Closed / Lapsed |