US3787818A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Mult-processor data processing system
Assignee: BAE Systems Defence Systems Ltd
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Filing: 1972-06-22
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Granted: 1974-01-22
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Expires: 1992-06-22
Abstract
Abstract A data processing system includes a group of peripheral units, a plurality of memory modules, a plurality of input-output channel units for use in providing access to the group of peripheral units and a plurality of processor modules. It also includes a plurality of separate data communication paths, one for each processor module and one for each input-output channel unit and each of the data communication paths is separately connected to all the storage modules and to at least one multiplex unit and each of the multiplex units is connected by an individual data transfer path to all the peripheral units of the group and all of the input-output channel units.
Inventors
- 👤 J Arnold
- 👤 G Beck
- 👤 R Boom
- 👤 M Ohalloran
- 👤 T Sandeman
- 👤 R Williams
- 👤 D Cosserat
- 👤 K Hodges
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 16:47
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/20; G06F11/2002; G06F11/2005; G06F11/2007; G06F13/00; G06F13/14; G06F13/20; G06F13/22; G06F15/00; G06F15/16
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
419 words
A data processing system comprising in combination: a plurality of processor modules; a plurality of data communication paths for each processor module allocated on a mutually exclusive basis and arranged to carry processor module generated address information; a plurality of multi-port access units each including a data communication path selection and terminating means and an identity address recognition means conditioned with a unique identity code and responsive to the reception of said unique identity code within said address information when applied to any one of said data communication paths; a plurality of memory modules each including an individual access unit and a group of peripheral equipments each said including an individual access unit and each peripheral equipment access unit includes a plurality of processor module accessible registers and an accessible register selection means responsive to part of said address information, and said accessible registers include: i. a first register into which processor module generated peripheral equipment control information is written by an interrogating processor module upon the activation of said identity address recognition means and said accessible register selection means in response to the application to said interrogating processor module''s data communication path of address information defining the identity of (a) the particular peripheral equipment and (b) said first register. ii. a second register from which peripheral equipment status information indicative of the current state of the particular peripheral equipment is read by an interrogating processor module upon the activation of said identity address recognition means and said accessible register selection means in response to the application to said interrogating processor module''s communication path of address information defining the identity of (a) the particular peripheral equipment and (b) said second register and either or both of iii. a third register into which data to be passed to said particular peripheral equipment is written by an interrogating processor module upon the activation of said identity address recognition means and said accessible register selection means in response to the application to said interrogating processor module''s data communication path of address information defining the identity of (a) the particular peripheral equipment and (b) said third register and iv. a fourth register from which data generated by said particular peripheral equipment is read by an interrogating processor module upon the activation of said identity address recognition means and said accessible register selection means in response to the application to said interrogating processor module''s data communication path of address information defining the identity of (a) the particular peripheral equipment and (b) said fourth register.
Claim 2
Dependent Claim
419 words
A data processing system comprising in combination: a plurality of processor modules; a plurality of data communication paths for each processor module allocated on a mutually exclusive basis and arranged to carry processor module generated address information; a plurality of multi-port access units each including a data communication path selection and terminating means and an identity address recognition means conditioned with a unique identity code and responsive to the reception of said unique identity code within said address information when applied to any one of said data communication paths; a plurality of memory modules each including an individual access unit and a group of peripheral equipments each said including an individual access unit and each peripheral equipment access unit includes a plurality of processor module accessible registers and an accessible register selection means responsive to part of said address information, and said accessible registers include: i. a first register into which processor module generated peripheral equipment control information is written by an interrogating processor module upon the activation of said identity address recognition means and said accessible register selection means in response to the application to said interrogating processor module''s data communication path of address information defining the identity of (a) the particular peripheral equipment and (b) said first register. ii. a second register from which peripheral equipment status information indicative of the current state of the particular peripheral equipment is read by an interrogating processor module upon the activation of said identity address recognition means and said accessible register selection means in response to the application to said interrogating processor module''s communication path of address information defining the identity of (a) the particular peripheral equipment and (b) said second register and either or both of iii. a third register into which data to be passed to said particular peripheral equipment is written by an interrogating processor module upon the activation of said identity address recognition means and said accessible register selection means in response to the application to said interrogating processor module''s data communication path of address information defining the identity of (a) the particular peripheral equipment and (b) said third register and iv. a fourth register from which data generated by said particular peripheral equipment is read by an interrogating processor module upon the activation of said identity address recognition means and said accessible register selection means in response to the application to said interrogating processor module''s data communication path of address information defining the identity of (a) the particular peripheral equipment and (b) said fourth register.
Claim 3
Dependent Claim
72 words
A data processing system as claimed in claim 1 wherein said system includes at least one multiplexor equipment provided with a multi-port access unit and each said data communication path is terminated upon an individual port of each multi-port memory module access unit and each multiplexor equipment access unit and each multiplexor equipment is connected by an individual data transfer path to an individual port on all the peripheral equipment access units.
Claim 4
Dependent Claim
84 words
A data processing system as claimed in claim 2 wherein said system includes at least one input/output channel module each arranged to independently handle information transfers between said peripheral equipments and said memory modules and each channel module is provided with a unique data communication path terminated upon an individual port of each multi-port memory module access unit and each multiplexor equipment access unit and each channel module includes an access unit upon a port of which each individual data transfer path is terminated.
Claim 5
Dependent Claim
37 words
A data processing system as claimed in claim 3 wherein each channel module access unit includes (i) a plurality of processor module accessible registers (ii) an identity address recognition means and (iii) an accessible register selection means.
Claim 6
Dependent Claim
85 words
A data processing system as claimed in claim 4 wherein each channel module includes a plurality of sets of channel registers each set being used to store transfer control information relative to a single transfer process and including (i) a channel control register (ii) transfer source and destination current address registers, (iii) a transit data word storage register and (iv) source and destination block identity registers and said channel module includes means for transferring information between said processor module accessible registers and said channel registers.
Claim 7
Dependent Claim
194 words
An input/output arrangement for use with a data processing system in which said arrangement includes a multi-stage switching network having on one side a plurality of input and control ports which are connected to a plurality of peripheral devices, and on the other side to a plurality of message handling devices and each switching stage indludes common control equipment which includes (i) means for cyclically inspecting said input ports for a demand condition and (ii) means for connecting, upon detection of a demand condition, the demanding input port to a control port to pass the demand condition on towards a free message handling device which is taken into use for the reception of a message comprising data and address information, and each switching stage further includes address generation means arranged to generate an address portion indicative of the switching stage port over which the demand was extended and said address generation means includes address transmission means arranged to transmit said address portion immediately following the information stream received from the demanding peripheral device, and said message handling devices include means for buffering information messages passing between said input/output arrangements and said data processing system.
Claim 8
Dependent Claim
194 words
An input/output arrangement for use with a data processing system in which said arrangement includes a multi-stage switching network having on one side a plurality of input and control ports which are connected to a plurality of peripheral devices, and on the other side to a plurality of message handling devices and each switching stage indludes common control equipment which includes (i) means for cyclically inspecting said input ports for a demand condition and (ii) means for connecting, upon detection of a demand condition, the demanding input port to a control port to pass the demand condition on towards a free message handling device which is taken into use for the reception of a message comprising data and address information, and each switching stage further includes address generation means arranged to generate an address portion indicative of the switching stage port over which the demand was extended and said address generation means includes address transmission means arranged to transmit said address portion immediately following the information stream received from the demanding peripheral device, and said message handling devices include means for buffering information messages passing between said input/output arrangements and said data processing system.
Claim 9
Dependent Claim
81 words
An input/output arrangement as claimed in claim 6 wherein each switching stage common control equipment includes means for suspending the cyclic inspection of its input ports upon detection of a demand condition on its control port and means are provided in the common control equipment to employ a predetermined number of information bits of a subsequently transmitted information stream to select and activate a particular input port over which the remaining bits of the transmitted information stream are to be directed.
Claim 10
Dependent Claim
87 words
An input/output arrangement as claimed in claim 7 wherein one of said input ports on a switching stage is connected to a port enable register in common control equipment of that switching stage and said port enable register includes one bit for each of the remaining input ports on that switching stage and said port enable register is cycled in sympathy with the cycling of said input ports and a bit when in one state inhibits the acceptance of a demand condition on the corresponding input port.
Claim 11
Dependent Claim
56 words
An input/output arrangement as claimed in claim 8 and in which each switching stage common control equipment includes a pair of input port address counters which are driven in synchronism and said common control equipment also includes a comparator arranged to inhibit the operations of both of said counters when said counters are not in sympathy.
Claim 12
Dependent Claim
35 words
An input/output arrangement as claimed in claim 9 wherein each peripheral device includes a serial interface unit providing access to at least two switching network ports and including a plurality of information stream identifiable registers.
Claim 13
Dependent Claim
64 words
An input/output arrangement as claimed in claim 10 wherein said registers include (i) a control register into which peripheral device and serial interface unit control information is written, (ii) a status register from which current operational state information relative to the peripheral device and serial interface unit equipment is read and (iii) data register for reception or transmission of information over the input/output arrangement.
Claim 14
Dependent Claim
79 words
An input/output arrangement as claimed in claim 11 wherein communication through said input/output arrangement is by way of serial communication links each comprising three leads in each direction of transmission and in which one of said leads is used to carry said information stream, a second of said leads is used to indicate the idle or busy state of the link whereas the third of said leads is used to carry timing pulses for synchronisation of said information stream.
Claim 15
Dependent Claim
66 words
An input/output arrangement as claimed in claim 12 wherein each serial interface unit includes a linking arrangement to interconnect the third leads of a serial communication link and said message handling devices include means for generating timing pulses for connection to the third lead of the serial communication link outgoing from the message handling device to a serial interface unit for each direction of information transfer.
Claim 16
Dependent Claim
38 words
An input/output arrangement as claimed in claim 13 wherein said serial interface unit includes a change detection mechanism associated with said status register and arranged to provide an indication when a change occurs in said operational state information.
Claim 17
Dependent Claim
32 words
An input/output arrangement as claimed in claim 14 wherein the activation of said change detection mechanism activates means in said serial interface unit to initiate a demand condition to said switching network.
Claim 18
Dependent Claim
48 words
An input/output arrangement as claimed in claim 15 wherein said serial interface unit also includes a second change detection mechanism associated with said data register for transmission of information over the input/output arrangement and activation of said second change detection mechanism causes said demand condition to be initiated.
Claim 19
Dependent Claim
47 words
An input/output arrangement as claimed in claim 16 wherein said message handling devices include means for storing a plurality of messages and further means to prevent the acceptance of a message from any of said peripheral devices until all messages for said peripheral devices have been transmitted.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-21 | 1977-07-23 | 1978-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-21 | 1981-07-23 | 1982-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-21 | 1985-07-23 | 1986-01-22 | $7700.00 | Window Closed / Lapsed |