Patent US4190849A successfully refreshed from Google Patents.
US4190849A
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Electronic-beam programmable semiconductor device structure
Assignee: Motorola Solutions Inc
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Filing: 1977-09-19
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Granted: 1980-02-26
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Expires: 1997-09-19
Abstract
Abstract A semiconductor device structure is provided in which an electrically isolated or "floating" conductor is adapted to receive electric charge from an electron beam. The resultant stored charge provides the basis for useful electronic functions such as floating gate MOS read-only-memories.
Inventors
- 👤 Michael W. Powell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 10:08
CPC Classifications
H; H10; H10P; H10P34/00; H10P34/40; G; G11; G11C; G11C13/00; G11C13/04; G11C13/047; G11C5/00; G11C5/06; G11C5/066
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
151 words
An integrated semiconductor device including an insulated gate field effect transistor capable of being selectively programmed by an electron beam for use in a memory array, said transistor comprising: an electrically isolated gate electrode overlying a gate insulator layer which overlies a semiconductor substrate of a first conductivity type and disposed spatially between a source region and a spaced apart drain region of opposite conductivity type which form a pair of PN junctions in said substrate; an insulator layer overlying said gate electrode and being of a thickness to allow penetration of electrons from an electron beam to said gate electrode; a region in said substrate underlying said gate electrode, positioned between said source and drain regions and having a conductive state responsive to electrons stored on said gate electrode from said electron beam; and means on said substrate for accurately positioning said electron beam with respect to said gate electrode.
Claim 2
Dependent Claim
151 words
An integrated semiconductor device including an insulated gate field effect transistor capable of being selectively programmed by an electron beam for use in a memory array, said transistor comprising: an electrically isolated gate electrode overlying a gate insulator layer which overlies a semiconductor substrate of a first conductivity type and disposed spatially between a source region and a spaced apart drain region of opposite conductivity type which form a pair of PN junctions in said substrate; an insulator layer overlying said gate electrode and being of a thickness to allow penetration of electrons from an electron beam to said gate electrode; a region in said substrate underlying said gate electrode, positioned between said source and drain regions and having a conductive state responsive to electrons stored on said gate electrode from said electron beam; and means on said substrate for accurately positioning said electron beam with respect to said gate electrode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-02-25 | 1983-08-27 | 1984-02-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-02-25 | 1987-08-27 | 1988-02-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-02-25 | 1991-08-27 | 1992-02-26 | $7700.00 | Window Closed / Lapsed |