US3736571A
Expired / Lapsed
US
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Method and system for improved operation of conductor-insulator-semiconductor capacitor memory having increased storage capability
Assignee: Micro-Bit Corp
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Filing: 1971-02-10
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Granted: 1973-05-29
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Expires: 1991-02-10
Abstract
Abstract A computer memory system employing a planar metal-insulator semiconductor-metal memory capacitor sandwich for selectively storing an array of electric charges in the insulator near the insulator-semiconductor interface in patterns which are representative of binary encoded data. The method and system for initially uniformly charging the planar surface of the insulator of a memory capacitor employing p-type semiconductors with positive polarity electric charges, maintaining the positive electric charges at those data bit sites representative of binary ''''I''s'''' and removing positive charges at the binary ''''O'''' data sites to form non-charged areas of diameter D surrounding the binary O data bit sites where D is the equivalent or greater than several electron path diffusion lengths in the semiconductor. The positive charges are formed in the insulator layers by bombarding the insulator with an electron beam while maintaining a positive polarity electric field across the memory capacitor. At the data bit sites where binary ''''O''s'''' are to be written, a negative polarity field gradient is established across the capacitor while irradiating the selected bit site with the electron beam. At each bit site the electron beam is appropriately manipulated by causing it to trace out a circular path of diameter D>d where d is the diameter of the electron beam. By spacing the data bit sites apart a distance L>D where the center-to-center spacing distance L is on the order of 20 microns or less, a grid-like lattice of positive electric charges is formed at the insulatorsemiconductor interface which surrounds all of the data bit sites. This in turn induces a corresponding interconnected gridlike lattice layer of strongly inverted and highly conducting semiconductor adjacent to the insulator-semiconductor interface. This highly conductive inverted semiconductor lattice layer surrounds and interconnects substantially all of the positively charged data bit sites but is separated from the non-charged, binary O bit sites by the distance D/2 which is the equivalent of or > several electron path diffusion lengths in the semiconductor. In memory capacitors using n-type semiconductors, the inverse of the charge states in p-type semiconductors is employed. During reading, a read-out electron beam selectively probes the data bit sites while a substantially zero voltage or slightly negative bias potential is maintained across the memory capacitor. Upon probing a charged binary 1 bit site, electronhole pair carriers are formed and are separated by the electric field of a depletion region induced in semiconductor layer as a consequence of the positive charges. The electron current is conductively connected to the highly conducting grid-like inverted lattice layer in the semiconductor and results in a relatively large capacitor charging current to the memory capacitor and a corresponding large output signal. Upon impinging into a non-charged binary O data bit site, electron-hole pair carriers produced in the semiconductor by the electron beam recombine within the non-charged region of diameter D prior to reaching the strongly conducting, inverted, grid-like layer. Hence, at most only a minimal charging current to the memory capacitor is produced that is readily distinguished from the output current produced at the charged binary 1 data bit sites. Enhanced operation is obtained by pretreatment of thE semiconductor through gold doping or annealing in oxygen at the high temperatures in order to enhance recombination rates in the non-charged areas of diameter D. Treatment of the metalized face of the insulator that is subjected to the write-read electron beam to produce a metal thickness on the order of 2,000 A units plus or minus 500 A units results in overcoming undesired disturb effects produced by scattering electrons. By appropriate readrewrite techniques interaction on adjacent bit sites by scattering electrons can be minimized and long term degradation of the memory over a number of operating cycles prevented.
Inventors
- 👤 M Cohen
- 👤 J Moore
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 06:28
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/23
Claims Analysis
Total Claims: 43
Claim 1
Independent Claim
100 words
A memory system employing a planar conductive layerinsulator-semiconductor memory capacitor sandwich for selectively storing an array of electric charges in the insulator layer near the insulator-semiconductor interface in patterns which are representative of binary encoded data comprising means for initially uniformly charging the planar surface of the insulator with positive polarity electric charges, means for maintaining the positive electric charges at certain sites in the planar memory element, and means for removing positive charges to form non-charged enlarged regions of extent D surrounding other sites where D is of the order of an electron path diffusion length in the semiconductor.
Claim 2
Dependent Claim
100 words
A memory system employing a planar conductive layerinsulator-semiconductor memory capacitor sandwich for selectively storing an array of electric charges in the insulator layer near the insulator-semiconductor interface in patterns which are representative of binary encoded data comprising means for initially uniformly charging the planar surface of the insulator with positive polarity electric charges, means for maintaining the positive electric charges at certain sites in the planar memory element, and means for removing positive charges to form non-charged enlarged regions of extent D surrounding other sites where D is of the order of an electron path diffusion length in the semiconductor.
Claim 3
Dependent Claim
186 words
A memory system according to claim 1 wherein the positive polarity electric charges are formed in the insulator with means for producing and deflecting a penetrating beam of electrons that can be caused to impinge into the insulator layer selectively at the discrete sites or to scan uniformly along substantially the entire surface of the memory capacitor, and means for maintaining a positive electric field gradient across the memory element sandwich whereby the conductive and insulator layer is maintained positive with respect to the underlying semiconductor substrate while bombarding the memory capacitor with the electron beam, and wherein positive charges are selectively removed to form non-charged enlarged regions of extent D by directing the penetrating electron beam selectively to the location where the other sites are to be recorded, means for maintaining a negative polarity electric field gradient across the memory element sandwich while irradiating the selected sites with the electron beam, and means for appropriately manipulating the penetrating beam of electrons at the selected sites to form the non-charged regions of extent D of the order of an electron path diffusion length in the semiconductor.
Claim 4
Dependent Claim
124 words
A memory system according to claim 2 wherein the penetrating beam of electrons has a beam diameter d and the means for manipulating the beam of electrons comprises means for additionally deflecting the electron beam in an enlarged trace path at each non-charged site to form the enlarged regions of extent D>d following the selective deflection of the electron beam to the respective sites which are spaced apart by a center-to-center spacing distance L>D whereby a grid-like lattice of positive electric charges is retained and surrounds the sites at the insulator-semiconductor interface to thereby form a corresponding interconnected grid-like lattice layer in the semiconductor adjacent the insulator-semiconductor interface that is highly conductive and which surrounds and interconnects a substantial number of the charged sites.
Claim 5
Dependent Claim
205 words
A memory system according to claim 3 further including means for directing a reading electron beam of sufficient energy to penetrate into the region of the semiconductor layer adjacent the insulator-semiconductor interface and of diameter d<D to selectively probe the sites while maintaining an appropriate reading bias potential across the memory capacitor sandwich whereby upon probing a charged site, electron-hole pair carriers are formed and are separated by the electric field of a space charge region induced in the semiconductor layer as a consequence of the positive charges, the electron-hole current being conductively connected to the highly conducting grid-like lattice layer in the semiconductor which underlies and is formed by the interconnected grid-like lattice of positive charges surrounding all of the sites to thereby induce a relatively large charging current to the memory capacitor resulting in a large output signal, and whereby upon impinging into a non-charged site, electron-hole pair carriers produced in the semiconductor by the electron beam recombine within the non-charged enlarged region of extent D prior to reaching the strong conducting inverted grid-like lattice layer and hence results in at most a minimal charging current to the memory capacitor that is readily distinguished from the output current produced at the charged sites.
Claim 6
Dependent Claim
37 words
A memory system according to claim 4 further including means for automatically rewriting the charge condition at each site immediately following read-out of the site whereby the read-out process is made to be substantially non-destructive in nature.
Claim 7
Dependent Claim
64 words
A memory system according to claim 4 further including means for selectively writing in both positive charged and non-charged sites at each site location by appropriate trace manipulation of the electron beam in the presence of either a positive polarity or negative polarity biasing potential across the memory capacitor sandwich whereby either charged areas or non-charged enlarged regions of extent D>d selectively are formed.
Claim 8
Dependent Claim
96 words
A memory system according to claim 6 further including means for automatically centering and directing the writing electron beam of diameter d<D onto the center of the sites immediately following the writing of the enlarged region of extent D sites and bombarding the center of the enlarged regions of extent D sites with the electron beam while maintaining the bias potential across the memory capacitor of opposite polarity to that used in writing for a period comparable to the writing period whereby interaction on adjacent sites of the memory capacitor due to scattering electrons is minimized.
Claim 9
Dependent Claim
97 words
A memory system according to claim 3 further including means for automatically centering and directing the writing electron beam of diameter d<D onto the center of the sites immediately following the writing of the enlarged regions of extent D sites and bombarding the center of the enlarged region of extent D sites with the electron beam while maintaining the bias potential across the memory capacitor of opposite polarity to that used in writing for a period comparable to the writing period whereby interaction on adjacent sites of the memory capacitor due to the scattering electrons is minimized.
Claim 10
Dependent Claim
69 words
A memory system according to claim 7 further including means for automatically reversing the polarity of the bias applied to the memory capacitor after read-out at each site while maintaining the read-out electron beam impinging on the site for a length of time corresponding to that required during read-out of the site whereby interaction on the charge condition of adjacent sites due to scattering electrons during read-out is minimized.
Claim 11
Dependent Claim
69 words
A memory system according to claim 4 further including means for automatically reversing the polarity of the bias applied to the memory capacitor after read-out of each site while maintaining the read-out electron beam impinging on the site for a period of time corresponding to that required during read-out of the site whereby interaction on the charge condition of adjacent sites due to scattering electrons during read-out is minimized.
Claim 12
Dependent Claim
68 words
A memory system according to claim 9 wherein the conductive layer covering the insulator of the memory capacitor sandwich and through which the write-read electron beam passes during writing and read-out of the memory element, has a density of the order of 50 micrograms/cm2 to minimize the passage of scattering electrons through the conductive layer whereby disturb effects on the memory due to such scattering electrons is minimized.
Claim 13
Dependent Claim
29 words
A memory system according to claim 1 wherein the semiconductor layer is doped to reduce electron diffusion path lengths to a minimum within the semiconductor at the insulator-semiconductor interface.
Claim 14
Dependent Claim
56 words
A memory system according to claim 1 wherein the portion of the memory element sandwich comprised by the semiconductor and insulator is annealed in a gaseous ambient at high temperatures on the order of 800*C for a period of time sufficient to introduce large quantities of electron-hole recombination centers in the semiconductor at the insulator-semiconductor interface.
Claim 15
Dependent Claim
66 words
A memory system according to claim 4 wherein there are a plurality of individual memory capacitor sandwiches arrayed in a common target plane of an electron beam apparatus and the means for producing and deflecting the electron beam comprises a micro-deflection system having individual microlens deflection systems for each respective memory capacitor sandwich whereby recording and read-out of each memory capacitor sandwich can be individually controlled.
Claim 16
Dependent Claim
26 words
A memory system according to claim 6 further including read-rewrite cycle control means for automatically rewriting the data stored at each data bit site after read-out.
Claim 17
Dependent Claim
24 words
A memory system according to claim 15 further including refresh cycle control means for reading and completely rewriting data stored in the memory system.
Claim 18
Dependent Claim
92 words
A memory system according to claim 4 wherein the memory capacitor sandwich comprises a film of Al covering a layer of SiO2 thermally grown on a p-type silicon substrate having an ohmic contact and the Al film through which the write-read electron beam passes during writing and read-out of the memory element, is provided with a thickness of the order of 2,000 A + or - 500 A to minimize the passage of scattering electrons through the metal film whereby disturb effects on the memory due to such scattering electrons is minimized.
Claim 19
Dependent Claim
31 words
A memory system according to claim 17 wherein the semiconductor layer is doped with gold to reduce electron diffusion path lengths to a minimum within the semiconductor at the insulator-semiconductor interface.
Claim 20
Dependent Claim
54 words
A memory system accOrding to claim 17 wherein the portion of the memory element sandwich comprised by the semiconductor and insulator is annealed in oxygen at high temperatures on the order of 800*C for a period of time sufficient to introduce large quantities of electron-hole recombination centers in the semiconductor at the insulator-semiconductor interface.
Claim 21
Dependent Claim
146 words
In a memory system using a planar conductive layer-insulator-semiconductor memory capacitor sandwich of the type employing the presence or absence of electric charges at a plurality of data sites in the insulator layer near the insulator-semiconductor interface to thereby selectively establish the presence or absence of space-charge regions in the semiconductor layer adjacent the insulator-semiconductor interface under the data sites in accordance with binary data to be stored and subsequently read-out, the improvement comprising means for establishing an interconnected grid-like lattice of strongly inverted, highly conductive semiconductor through a substantial portion of the semiconductor layer at the insulator-semiconductor interface surrounding and interconnecting those sites where electric charges are stored, and means for maintaining the immediate enlarged region of extent D surrounding the remaining sites in a substantially non-inverted poorly conducting condition where D is of the order of an electron path diffusion length in the semiconductor.
Claim 22
Dependent Claim
146 words
In a memory system using a planar conductive layer-insulator-semiconductor memory capacitor sandwich of the type employing the presence or absence of electric charges at a plurality of data sites in the insulator layer near the insulator-semiconductor interface to thereby selectively establish the presence or absence of space-charge regions in the semiconductor layer adjacent the insulator-semiconductor interface under the data sites in accordance with binary data to be stored and subsequently read-out, the improvement comprising means for establishing an interconnected grid-like lattice of strongly inverted, highly conductive semiconductor through a substantial portion of the semiconductor layer at the insulator-semiconductor interface surrounding and interconnecting those sites where electric charges are stored, and means for maintaining the immediate enlarged region of extent D surrounding the remaining sites in a substantially non-inverted poorly conducting condition where D is of the order of an electron path diffusion length in the semiconductor.
Claim 23
Dependent Claim
68 words
A memory system according to claim 20 wherein the conductive layer covering the insulator of the memory capacitor sandwich and through which the write-read electron beam passes during writing and read-out of the memory element, has a density of the order of 50 micrograms/cm2 to minimize the passage of scattering electrons through the conductive layer whereby disturb effects on the memory due to such scattering electrons is minimized.
Claim 24
Dependent Claim
29 words
A memory system according to claim 20 wherein the semiconductor layer is doped to reduce electron diffusion path lengths to a minimum within the semiconductor at the insulator-semiconductor interface.
Claim 25
Dependent Claim
56 words
A memory system according to claim 20 wherein the portion of the memory element sandwich comprised by the semiconductor and insulator is annealed in an oxygen atmosphere at high temperatures on the order of 800*C for a period of time sufficient to introduce large quantities of electron-hole recombination center in the semiconductor at the insulator-semiconductor interface.
Claim 26
Dependent Claim
66 words
A memory system according to claim 20 wherein there are a plurality of individual memory capacitor sandwiches arrayed in a common target plane of an electron beam apparatus and the means for producing and deflecting the electron beam comprises a microdeflection system having individual micro-lens deflection system for each respective memory capacitor sandwich whereby recording and read-out of each memory capacitor sandwich can be individually controlled.
Claim 27
Independent Claim
91 words
The method of operating a memory system employing a planar conductive layer insulator-semiconductor memory capacitor sandwich for selectively storing electric charges in the insulator near the insulator-semiconductor interface in patterns which are representative of data to be stored, comprising initially uniformly charging the planar surface of the insulator with positive polarity electrical charges, selectively maintaining positive polarity electrical charges at certain sites and selectively discharging the immediate enlarged regions of extent D surrounding the remaining sites where D is of the order of an electron path diffusion length in the semiconductor.
Claim 28
Independent Claim
91 words
The method of operating a memory system employing a planar conductive layer insulator-semiconductor memory capacitor sandwich for selectively storing electric charges in the insulator near the insulator-semiconductor interface in patterns which are representative of data to be stored, comprising initially uniformly charging the planar surface of the insulator with positive polarity electrical charges, selectively maintaining positive polarity electrical charges at certain sites and selectively discharging the immediate enlarged regions of extent D surrounding the remaining sites where D is of the order of an electron path diffusion length in the semiconductor.
Claim 29
Dependent Claim
206 words
The method according to claim 25 wherein positive polarity electric charges are formed in the insulator by subjecting the memory element sandwich to a penebeam of radiant energy of sufficient energy to impinge into the insulator layer while simultaneously applying a positive electric field gradient across the memory capacitor sandwich in a direction such that the conductive layer and insulatOr are positive with respect to the semiconductor substrate, and wherein the positive charges selectively are discharged within the enlarged regions of extent D by subjecting the memory element sandwich to the penetrating beam of radiant energy while appropriately manipulating the beam and while applying a negative polarity electric field gradient across the memory element sandwich in a direction such that the conductive layer and insulator are negative with respect to the semiconductor substrate, the sites being spaced apart a distance L>D whereby an interconnected grid-like lattice of positive charges is established throughout a substantial portion of the surface of the insulator surrounding the charged sites at the insulator-semiconductor surface to thereby form a corresponding interconnected grid-like lattice layer of strongly inverted highly conducting semiconductor adjacent the insulator-semiconductor interface surrounding and interconnecting the charged sites but not connected to the non-charged enlarged region sites of extent D.
Claim 30
Dependent Claim
107 words
The method according to claim 26 wherein the penetrating beam of radiant energy comprises an electron beam having a beam diameter d<D<L and sufficient energy to penetrate through the upper conductive layer and into the insulator and the electron beam is suitably deflected in a trace path to form the enlarged regions of extent D>d and spaced apart by a center-to-center spacing distance L>D where D is of the order of an electron diffusion path in the semiconductor, and results in establishing the interconnected grid-like lattice of positive charges throughout a substantial portion of the surface of the insulator surrounding the charged sites at the insulator-semiconductor interface.
Claim 31
Dependent Claim
197 words
A method according to claim 27 further including reading out the previously stored data with a reading electron beam of diameter d<D and of sufficient energy to penetrate into the region of the semiconductor layer adjacent the insulator-semiconductor interface whereby upon the reading electron beam impinging upon positively charged sites, electron-hole pair carriers are formed in a space charge region existing in the semiconductor under the positively charged sites and result in the production of an electron-hole current flow that is interconnected with the highly conductive grid-like inversion layer lattice formed in the semiconductor adjacent the insulator-semiconductor interface to produce a large charging current flow across the memory capacitor sandwich that is distinctive to the positively charged sites, and whereby upon the reading electron beam impinging upon non-charged areas of the insulator, electron-hole pair carriers generated in the semiconductor are strongly attenuated due to recombination before diffusing to the highly conductive interconnected inversion layer lattice as a result of the enlarged region of extent D being of the order of an electron diffusion path length to thereby produce little or no output charging current flow across the memory element sandwich that is distinctive of the non-charged sites.
Claim 32
Dependent Claim
81 words
The method according to claim 28 wherein data represented by positive charges at certain sites is written in the same manner as data represented by non-charged sites by maintaining a positive polarity voltage gradient across the memory capacitor sandwich while simultaneously directing the writing beam of penetrating radiation onto the site and manipulating the beam in an enlarged trace path to assure formation of positively charged sites of enlarged region of extent D interconnected with the grid-like lattice of positive charges.
Claim 33
Dependent Claim
35 words
The method of claim 29 further including automatically rewriting the charge or non-charge condition at each site immediately following read-out of the site whereby the read-out process is made to be substantially non-destructive in nature.
Claim 34
Dependent Claim
95 words
The method of claim 29 further including automatically centering and directing the writing elecTron beam of diameter d<D onto the center of the sites immediately following writing of the enlarged region of extend D sites and irradiating the center of the enlarged region of extent D sites with the electron beam while maintaining the bias potential across the memory capacitor sandwich of opposite polarity to that used in writing the site for a period of time comparable to the original writing period whereby interaction on adjacent sites due to scattering electrons during writing is minimized.
Claim 35
Dependent Claim
66 words
The method according to claim 31 further including automatically reversing the polarity of the bias applied to the memory capacitor after read-out of each site while maintaining the read-out electron beam impinging on the site for a period of time corresponding to that required during read-out of the site whereby interaction on the charge condition of adjacent sites due to scattering electrons during read-out is minimized.
Claim 36
Dependent Claim
26 words
The method according to claim 28 further including automatically refreshing the memory by reading-out and rewriting each site during periods of non-use by the computer system.
Claim 37
Dependent Claim
29 words
The method according to claim 28 further including automatically reading-out and completely rewriting the memory starting with uniformly charging the memory capacitor after a predetermined number of operating cycles.
Claim 38
Dependent Claim
31 words
The method according to claim 28 further including pretreating the semiconductor to enhance recombination of the electron-hole pair carriers within the non-charged sites formed by the enlarged region of extent D.
Claim 39
Dependent Claim
31 words
The method according to claim 28 further including pretreating the semiconductor to enhance recombination of the electron-hole pair carriers within the non-charged sites formed by the enlarged region of extent D.
Claim 40
Dependent Claim
41 words
The method of claim 35 further including forming the conductive layer covering the insulator surface exposed to the electron beam in a manner to provide a density of the order of 50 micrograms/cm2 to minimize the disturb effect of scattered electrons.
Claim 41
Dependent Claim
41 words
The method of claim 36 further including forming the conductive layer covering the insulator surface exposed to the electron beam in a manner to provide a density of the order of 50 micrograms/cm2 to minimize the disturb effect of scattered electrons.
Claim 42
Dependent Claim
34 words
The method of claim 37 further including treating the internal surfaces of an electron-optical column that forms the write-read electron beam with materials of low back scatter coefficient to minimize multiple scattered electron reflections.
Claim 43
Dependent Claim
34 words
The method of claim 38 further including treating the internal surfaces of an electron-optical column that forms the write-read electron beam with materials of low back scatter coefficient to minimize multiple scattered electron reflections.
References Cited (Backward Citations)
US3623026A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-05-28 | 1976-11-27 | 1977-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-05-28 | 1980-11-27 | 1981-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-05-28 | 1984-11-27 | 1985-05-29 | $7700.00 | Window Closed / Lapsed |