Control system for central processing unit with plural execution units

Claim 2

In a control system for a central processor having a first execution unit for executing a plurality of instructions and a plurality of instruction control units coupled to said first execution unit for controlling the transfer of instructions to said first execution unit, wherein said first execution unit is shared by said plurality of instruction control units, the improvement wherein said first execution unit executes a first group of instructions transferred from said plurality of instruction control units, said control system includes a plurality of second execution units, each of which is provided correspondingly and is connected to a respective one of said instruction control units and each of which executes a second group of instructions which have a higher frequency of use than said first group of instructions, and said each of said instruction control units includes first means for indicating whether an instruction under control of a respective one of said instruction control units belongs to said second group of instructions, and second means, responsive to said first means, for transferring an instruction to be executed, which belongs to said first group, to said first execution unit and for transferring an instruction to be executed, which belongs to said second group, to a corresponding one of said second execution units.

Claim 3

The improvement according to claim 1, wherein said control system comprises third means for indicating whether or not said first execution unit is being used, and wherein each of said instruction control units comprises fourth means for indicating whether or not said corresponding second execution unit is being used, fifth means connected to said first and third means for transferring an instruction to be executed to said first execution unit is response to said first and third means indicating that said instruction to be executed belongs to said first group and that said first execution unit is not being used, and sixth means, connected to said first and fourth means, for transferring an instruction to be executed to said corresponding second execution unit in response to said first and fourth means indicating that said instruction to be executed belongs to said second group and that said corresponding second execution unit is not being used.

Claim 4

The improvement according to claim 1, in which each of said instruction control units comprises a plurality of instruction buffer registers for storing instructions to be executed, an instruction register for storing an instruction from said instruction buffer registers, a decoder for decoding an instruction and indicating that said instruction stored in said instruction register belongs to said second group, a plurality of instruction queue registers for storing instructions from said instruction register, and a controller for controlling the transfer of an instruction from one of said instruction queue registers to only one of said first and second execution units in response to the indication by said decoder.

Claim 5

In a computer comprising a main memory for storing instructions and a central processor having a memory control unit connected to said main memory for deriving instructions to be executed from said main memory, a first execution unit for executing instructions and a plurality of instruction control units which are connected to said memory control unit and said first execution unit and which share said first execution unit, the improvement wherein said first execution unit executes a first group of instructions transferred from said plurality of instructions control units, said control system includes a plurality of second execution units, each of which is provided correspondingly and is connected to a respective one of said instruction control units and each of which executes a second group of instructions which have a higher frequency of use than said first group of instructions, and said each of said instruction control units includes first means for indicating whether an instruction under control of a respective one of said instruction control units belongs to said second group of instructions, and second means, responsive to said first means, for transferring an instruction to be executed, which belongs to said first group, to said first execution unit, and for transferring an instruction to be executed, which belongs to said second group, to a corresponding one of said second execution units.

Claim 6

In a computer comprising a main memory for storing instructions and a central processor having a memory control unit connected to said main memory for deriving instructions to be executed from said main memory, a first execution unit for executing instructions and a plurality of instruction control units which are connected to said memory control unit and said first execution unit and which share said first execution unit, the improvement wherein said first execution unit executes a first group of instructions transferred from said plurality of instructions control units, said control system includes a plurality of second execution units, each of which is provided correspondingly and is connected to a respective one of said instruction control units and each of which executes a second group of instructions which have a higher frequency of use than said first group of instructions, and said each of said instruction control units includes first means for indicating whether an instruction under control of a respective one of said instruction control units belongs to said second group of instructions, and second means, responsive to said first means, for transferring an instruction to be executed, which belongs to said first group, to said first execution unit, and for transferring an instruction to be executed, which belongs to said second group, to a corresponding one of said second execution units.

Claim 7

The improvement according to claim 4, which further includes an input/output processor, connected to said first and second execution units to which the result of the execution operation carried out by said execution units is transferred.

Claim 8

The improvement according to claim 4, in which each one of said instruction control units comprises storing means, connected to said memory control unit, for storing an instruction to be executed transferred from said memory control unit, and controlling means, connected to said storing means and said first and second execution units, for controlling the transfer of the instruction stored in said storing means to only one of said first and second execution units in response to whether or not the instruction corresponds to the certain kinds of instructions which can be executed by said second execution unit and whether or not said first execution unit and said corresponding one of said second execution units are being used.