US3701976A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Floating point arithmetic unit for a parallel processing computer
Assignee: AT&T Inc
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Filing: 1970-07-13
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Granted: 1972-10-31
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Expires: 1990-07-13
Abstract
Abstract A digital array data processor having a plurality of substantially identical processing units is described. Each processing unit includes a floating point arithmetic unit which performs arithmetic operations based on control signals sent on a common bus to each processing unit. The arithmetic unit further includes a single step combinatorial shifting circuit for aligning and normalizing operands.
Inventors
- 👤 Richard Robert Shively
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:20
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/483; G06F7/485; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F15/8015; G06F5/00; G06F5/01; G06F5/012; G06F2207/00; G06F2207/38; G06F2207/48; G06F2207/4802; G06F2207/4804; G06F7/499; G06F7/49936
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
115 words
A multiprocessor data processing system comprising a source of global control signals, and a plurality of arithmetic units responsive to said global control signals, said arithmetic units each comprising A. a memory for storing a plurality of operands, B. an adder for generating a sum signal representing the algebraic sum of pairs of operands having a predetermined format, C. a parallel shifter responsive to applied control signals for shifting at least one of said operands, said shifting being accomplished as a single step with substantially constant delay regardless of the extent of the required shift, thereby generating output operands having said predetermined format, and D. means for applying said output operands to said arithmetic unit.
Claim 2
Dependent Claim
115 words
A multiprocessor data processing system comprising a source of global control signals, and a plurality of arithmetic units responsive to said global control signals, said arithmetic units each comprising A. a memory for storing a plurality of operands, B. an adder for generating a sum signal representing the algebraic sum of pairs of operands having a predetermined format, C. a parallel shifter responsive to applied control signals for shifting at least one of said operands, said shifting being accomplished as a single step with substantially constant delay regardless of the extent of the required shift, thereby generating output operands having said predetermined format, and D. means for applying said output operands to said arithmetic unit.
Claim 3
Dependent Claim
24 words
means for applying said output signals for each subunit as inputs to the subunit corresponding to the next less significant digit in said sum.
Claim 4
Dependent Claim
24 words
means for applying said output signals for each subunit as inputs to the subunit corresponding to the next less significant digit in said sum.
Claim 5
Dependent Claim
29 words
A system as in claim 1 wherein said arithmetic units further comprise means for applying said sum signal to said adder in place of one of said two operands.
Claim 6
Dependent Claim
31 words
means for normalizing said sum independently of processing in any other processing unit, said normalizing being effected in respective ones of said processing units regardless of the extent of normalization required.
Claim 7
Dependent Claim
31 words
means for normalizing said sum independently of processing in any other processing unit, said normalizing being effected in respective ones of said processing units regardless of the extent of normalization required.
Claim 8
Dependent Claim
18 words
A system as in claim 1 wherein said arithmetic unit further comprises means for normalizing said sum signals.
Claim 9
Dependent Claim
23 words
A system as in claim 1 further comprising a source of normalization signals and wherein said shifter is responsive to said normalization signals.
Claim 10
Dependent Claim
41 words
A system as in claim 4 wherein said source of normalization signals comprises means for generating a coded representation of the number of digit positions between the sign digit and the most significant digit which is different from said sign digit.
Claim 11
Dependent Claim
15 words
A system as in claim 5 wherein said means for generating a coded representation comprises
Claim 12
Dependent Claim
47 words
Apparatus as in claim 5 further comprising in said means for generating coded representation A. a source of signals B. a plurality of output lines, and C. means responsive to said second ordered values for connecting said source of signals to selected ones of said output lines.
Claim 13
Independent Claim
113 words
A system for adding first and second comprising A. an adder for forming sum signals indicating the sum of applied operands, B. a shifter for parallel shifting a word representing a number through a predetermined number of digit positions, said shifting being accomplished in parallel for all digits of said number and at a substantially constant rate regardless of the extent of the required shift, C. means for applying said numbers to said shifter in sequence, D. means for directing that said shifter perform a specified shift on each of said numbers thereby forming first and second shifted numbers, and E. means for applying said first and second shifted numbers to said adder.
Claim 14
Independent Claim
113 words
A system for adding first and second comprising A. an adder for forming sum signals indicating the sum of applied operands, B. a shifter for parallel shifting a word representing a number through a predetermined number of digit positions, said shifting being accomplished in parallel for all digits of said number and at a substantially constant rate regardless of the extent of the required shift, C. means for applying said numbers to said shifter in sequence, D. means for directing that said shifter perform a specified shift on each of said numbers thereby forming first and second shifted numbers, and E. means for applying said first and second shifted numbers to said adder.
Claim 15
Dependent Claim
85 words
A system according to claim 8 further comprising A. a normalizing circuit for generating normalizing signals indicating the number digit positions through which a number must shifted to conform to a standard format, B. means for applying said sum signals to said normalizing circuit, and C. means for applying said normalizing signals corresponding to said sum signals to said shifter, D. meAns for applying said sum to said shifter, whereby said shifter generates an output signal corresponding to a normalized version of said sum signals.
Claim 16
Dependent Claim
11 words
A computer system comprising a plurality of processing units each comprising
Claim 17
Dependent Claim
11 words
A computer system comprising a plurality of processing units each comprising
Claim 18
Dependent Claim
46 words
A system as in claim 10 wherein said means for normalizing includes a parallel shifter responsive to coded shift signals, and means for generating coded shift signals indicating the number of digit positions through which said sum must be shifted to effect normalization of said sum.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-31 | 1976-05-01 | 1976-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-31 | 1980-05-01 | 1980-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-31 | 1984-05-01 | 1984-10-31 | $7700.00 | Window Closed / Lapsed |