Digital monitor having memory readout by the monitored system

Claim 1

Apparatus for monitoring the operation of a synchronous digital system to detect malfunctions thereof, comprising in combination: (a) memory means having stored therein at first predetermined storage locations a first predetermined group of digital numbers comprising a sequence of numbers ranging in value from 1 to m with each storage location being identified by a digital number having a bit pattern corresponding to a bit pattern generated by said synchronous system when said system is operating normally and stored therein at the remaining memory locations a second predetermined group of digital numbers, said first and second predetermined groups of digital numbers being mutually exclusive; (b) read means for sequentially reading digital numbers from said memory means utilizing a series of digital bit patterns generated by the system being monitored as addresses; (c) a digital counter and means for incrementing said digital counter one count each time a digital number containing at least one logic "one" bit is read from said memory means to generate and store in said digital counter a number corresponding to the number of words containing at least one logic "one" bit which are read from said memory means; and (d) first compare means for comparing said digital numbers from said memory means to the number stored in said digital counter to generate a first error signal when the data output of said memory means and said number stored in said digital counter are not identical.