Method and apparatus for fault testing a digital computer memory

Claim 2

A digital computer memory having a given numerical address code, comprising: storage means including a plurality of test data word storage locations collectively containing a plurality of test data words identical to a plurality of test address words identifying the test data word storage locations, the test address words collectively including all coefficients of all powers of the radix of the given numerical address code; address means connected to the storage means for accessing the test data word storage locations in response to the receipt of the test address words identifying the test data word storage locations; generator means connected to the address means for generating the test address words and transferring them to the address means so as to access the test data word storage locations identified by the test address words; readout means connected to the storage means for retrieving the test data words contained within the test data word storage locations accessed by the address means; and comparator means connected to the readout means and to the address means for detecting any difference between the generated test address words and the retrieved test data words thereby to indicate the presence of a fault within the computer memory.

Claim 3

A digital computer memory having a given numerical address code, comprising: storage means including a plurality of test data word storage locations each containing a test data word identical to a related test address word which identifies the test data word storage location, the test address words collectively including all coefficients of all powers of the radix of the given numerical address code; address means connected to the storage means for accessing the test data word storage locations in response to the receipt of the test address words identifying the test data word storage locations; generator means connected to the address means for generating the test address words and for transferring the generated test address words to the address means so as to access the test data word storage locations identified by the generated test address words; readout means connected to the storage means for retrieving the test data words contained within the test data word storage locations accessed by the address means; and comparator means connected to the readout means and to the address means for comparing the discrete digital bits of related ones of the generated test address words and the retrieved test data words thereby to monitor the operation of the computer memory as a function of the correspondence between the digital bits of the test words.

Claim 4

A digital computer memory having a given numerical address code, comprising: storage means including a plurality of test data word storage locations each containing a test data word identical to a related test address word which identifies the test data word storage location, the test address words collectively including all coefficients of all powers of the radix of the given numerical address code; address means connected to the storage means for accessing the test data word storage locations in response to the receipt of the test address words identifying the test data word storage locations; generator means connected to the address means for generating the test address words and for transferring the generated test address words to the address means so as to access the test data word storage locations identified by the generated test address words; readout means connected to the storage means for retrieving the test data words contained within the test data word storage locations accessed by the address means; and comparator means connected to the readout means and to the address means for comparing the discrete digital bits of related ones of the generated test address words and the retrieved test data words thereby to monitor the operation of the computer memory as a function of the correspondence between the digital bits of the test words.

Claim 5

A digital computer memory as recited in claim 2 including write-in means connected to the storage means for inserting the test data words retrieved by the readout means back within the test data word storage locations accessed by the address means.

Claim 6

A digital computer memory having a given numerical address code comprising: storage means including a plurality of test data word storage locations each containing a test data word identical to a related test address word identifying the test data word storage location, the test address words collectively including all coefficients of all powers of the radix of the given numerical address code; address means connected with the storage means and including memory selector means having a plurality of selection circuits energizable in various combinations for accessing the test data word storage locations in response to the receipt of the test address words identifying the test data word storage locations, each power of the radix of the numerical address code regulating the energization of a particular group of selection circuits and each coefficient of each power of the radix of the numerical address code controlling the energization of a specific selection circuit within each particular group so that all of the selection circuits are exercised by the test address words; generator means connected with the address means for generating thE test address words and for transferring the generated test address words to the address means so as to access the test data word storage locations identified by the generated test address words; readout means connected with the storage means for retrieving the test data words contained within the accessed test data word storage locations; and comparator means connected with the readout means and with the address means for detecting any noncorrespondence between the discrete digital bits of related ones of the generated test address words and the retrieved test data words thereby to monitor the operation of the computer memory as a function of the correspondence between the digital bits of the test words.

Claim 7

A digital computer memory having a given numerical address code comprising: storage means including a plurality of test data word storage locations each containing a test data word identical to a related test address word identifying the test data word storage location, the test address words collectively including all coefficients of all powers of the radix of the given numerical address code; address means connected with the storage means and including memory selector means having a plurality of selection circuits energizable in various combinations for accessing the test data word storage locations in response to the receipt of the test address words identifying the test data word storage locations, each power of the radix of the numerical address code regulating the energization of a particular group of selection circuits and each coefficient of each power of the radix of the numerical address code controlling the energization of a specific selection circuit within each particular group so that all of the selection circuits are exercised by the test address words; generator means connected with the address means for generating thE test address words and for transferring the generated test address words to the address means so as to access the test data word storage locations identified by the generated test address words; readout means connected with the storage means for retrieving the test data words contained within the accessed test data word storage locations; and comparator means connected with the readout means and with the address means for detecting any noncorrespondence between the discrete digital bits of related ones of the generated test address words and the retrieved test data words thereby to monitor the operation of the computer memory as a function of the correspondence between the digital bits of the test words.

Claim 8

A digital computer memory as recited in claim 4 including write-in means connected with the storage means for inserting the test data words retrieved by the readout means back into the test data word storage locations accessed by the address means.

Claim 9

A digital computer memory as recited in claim 4 wherein the generator means successively develops each succeeding test address word by relatively shifting the digital bits of each preceding test address word in a predetermined repeatable manner, and the comparator means serially compares the discrete digital bits of each test address word with the discrete digital bits of each related test data word so as to detect any noncorrespondence between the digital bits of the test words thereby to indicate the presence of a fault within the computer memory.

Claim 10

A digital computer memory as recited in claim 4 including fault monitor means for identifying the particular test address word and test data word giving rise to a detected noncorrespondence between their digital bits.