US3599146A
Expired / Lapsed
US
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Memory addressing failure detection
Assignee: RCA Corp
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Filing: 1968-04-19
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Granted: 1971-08-10
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Expires: 1988-04-19
Abstract
Abstract A system for detecting errors in the operation of a random access memory which is particularly useful in memories employing semiconductor decoder elements and semiconductor memory elements. Each word storage location in the memory contains a memory address parity bit for the address of that word storage location. When a word storage location is accessed for readout, the parity bit of the memory address employed is compared with the memory address parity bit stored in the word location. If the bits are different, an error signal is generated.
Inventors
- 👤 Joseph A Weisbecker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 01:02
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/1016; G06F11/1032
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
113 words
In a random access memory system having addressable word storage locations, the combination of a source of memory addresses each having an associated memory address parity bit, decoder means utilizing a memory address from said source to address a word storage location in the memory, means operative when writing information into an addressed word storage location to store the associated address parity bit in the addressed word storage location, and means operative when reading information from an addressed word storage location to compare the parity bit of the memory address employed with the parity bit read out from the addressed word location, and to generate an error signal if the bits are different.
Claim 2
Dependent Claim
113 words
In a random access memory system having addressable word storage locations, the combination of a source of memory addresses each having an associated memory address parity bit, decoder means utilizing a memory address from said source to address a word storage location in the memory, means operative when writing information into an addressed word storage location to store the associated address parity bit in the addressed word storage location, and means operative when reading information from an addressed word storage location to compare the parity bit of the memory address employed with the parity bit read out from the addressed word location, and to generate an error signal if the bits are different.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-09 | 1975-02-08 | 1975-08-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-09 | 1979-02-08 | 1979-08-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-09 | 1983-02-08 | 1983-08-10 | $7700.00 | Window Closed / Lapsed |