High speed data transfer for a peripheral controller

Claim 2

A controller intermediate a central processor and a peripheral device having a data storage register from and to which device data is transferred through adaptor ports between the processor and controller and between the controller and the device during the same operation cycle, said controller including a plurality of device adaptor ports providing an interface for peripheral devices and a plurality of link adaptor ports for providing an interface for a central processor, comprising A. an interFace bus connected to all adaptor, ports having portions for input and output data transfer connected to said controller data storage register; B. an adaptor number register for selecting an adaptor port for data transfer; C. a control register for associating a link adaptor port with a controller adaptor port; D. first selection logic means responsive to said adaptor number register for selecting an device adaptor port for data transfer on said interface bus; E. second selection logic means responsive to said adaptor number register and said control register for selecting a link adaptor port for data transfer on said interface bus.

Claim 3

The apparatus of claim 1, further comprising: F. a read/write memory, connected to said interface bus, for selectively receiving data.

Claim 4

The apparatus of claim 1, further comprising: F. interconnection means, connecting a link adaptor port and a device adaptor port, for enabling a response-in signal from the device adaptor through the link adaptor port to indicate that a data transfer has been successful.

Claim 5

In a programmed peripheral controller responsive to adaptor service requests, apparatus for enabling data transfers between a pair of adaptor ports during a single instruction cycle, said controller including a plurality of link adaptor ports and a plurality of controller adaptor ports, comprising: A. a pair of bistable controller register elements for associating a pair of link adaptor ports with a pair of controller adaptor ports in accordance with the respective states of said pair of bistable register elements; B. an accumulator register; C. an input switch for selectively loading said accumulator; D. a common input data bus connected to said input switch and connected to all adaptor ports; E. a common output data bus connected to all adaptor ports; F. an output switch selectively connecting said accumulator to said output data bus; G. a pair of bistable adaptor number register elements; H. interrupt logic for selectively setting said pair of bistable adaptor number register elements; I. a control store output register for receiving controller adaptor service requests; J. primary adaptor port selection logic, responsive to said pair of bistable controller register elements and to said pair of bistable number register elements; K. auxiliary adaptor port selection logic, responsive to pair of bistable controller register elements, to said pair of bistable number register elements, and to said control store output register.

Claim 6

In a programmed peripheral controller responsive to adaptor service requests, apparatus for enabling data transfers between a pair of adaptor ports during a single instruction cycle, said controller including a plurality of link adaptor ports and a plurality of controller adaptor ports, comprising: A. a pair of bistable controller register elements for associating a pair of link adaptor ports with a pair of controller adaptor ports in accordance with the respective states of said pair of bistable register elements; B. an accumulator register; C. an input switch for selectively loading said accumulator; D. a common input data bus connected to said input switch and connected to all adaptor ports; E. a common output data bus connected to all adaptor ports; F. an output switch selectively connecting said accumulator to said output data bus; G. a pair of bistable adaptor number register elements; H. interrupt logic for selectively setting said pair of bistable adaptor number register elements; I. a control store output register for receiving controller adaptor service requests; J. primary adaptor port selection logic, responsive to said pair of bistable controller register elements and to said pair of bistable number register elements; K. auxiliary adaptor port selection logic, responsive to pair of bistable controller register elements, to said pair of bistable number register elements, and to said control store output register.

Claim 7

The apparatus of claim 4, further comprising: L. a read/write memory, connected to said interface bus, for selectively receiving data.

Claim 8

The apparatus of claim 4, further comprising: L. interconnection means, connecting a link adaptor port and a controller adaptor port, for enabling a response-in signal from the controller adaptor through the link adaptor port to indicate that a data transfer has been successful.