Method and apparatus for controlling a multiprocessor system

Claim 2

A multiprocessing system comprising: a plurality of computers, a plurality of memory sections, a time multiplexed bus system interconnecting said computers with said memory sections, computer polling means for repetitively and sequentially polling said computers to determine whether any one of said polled computers currently, requires access to any one of said memory sections, computer gating means responsive to a determination that a polled computer currently requires said access for connecting said polled computer over said bus system to said one memory section for a time interval controlled by said computer polling means, means in said polled computer for transmitting service request information to said one memory section over said bus system during said time interval, memory polling means for repetitively and sequentially polling said memory sections to determine whether any one of said polled memory sections currently requires access to any one of said computers, said memory polling means being asynchronously operated with respect to said computer polling means, memory gating means responsive to a determination that a polled memory section currently requires access to one of said computers for connecting said polled memory section over said bus system to said one computer for a time interval controlled by said memory polling means, and means for transmitting information over said bus system between said polled memory section and said one computer during said last named time interval.

Claim 3

The system of claim 1 wherein said computer polling means comprises: means for generating computer timing pulses, means responsive to the generation of said computer timing pulses for repetitively interrogating said computers sequentially one at a time, and means for enabling said computer gating means when an interrogated computer requires access to a memory section.

Claim 4

The system of claim 2 wherein said means for interrogating said computers comprises: means responsive to said computer timing pulses for repetitively generating a sequence of different identity codes with each code being unique to a different one of said computers, means for applying each generated code to all of said computers, and means in each of said computers responsive to the receipt of its identity code for activating its gating means.

Claim 5

The system of claim 3 wherein said memory polling means comprises: means for generating memory timing pulses, means responsive to the generation of said memory timing pulses for repetitively interrogating said memory sections sequentially one at a time, and means for enabling said memory gating means when an interrogated memory section requires access to one of said computers.

Claim 6

The system of claim 4 wherein said means for interrogating said memory sections comprises: means responsive to said memory timing pulses for repetitively generating a sequence of different identity codes with each code being unique to a different one of said memory sections, means for applying each generated memory identity code to all of said memory sections, and means in each of said memory sections responsive to the receipt of its identity code for activating its gating means.

Claim 7

A multiprocessing system comprising: a plurality of computers, a plurality of memory sections, a plurality of time multiplexed buses interconnecting said computers with said memory sections, computer polling means for repetitively and sequentially polling said computers to determine whether any one of said polled computers currently requires access to any one of said memory sections, computer gating means responsive to a determination that one of said polled computers currently requires access to one of said memory sections for gating service request information from said one computer onto a first set of said buses for transmission to said one memory section, said service request information including the identity codes of said one computer and said one memory section, means in said one memory section for storing said transmitted information except for said one memory section identity code, memory polling means for repetitively and sequentially polling said memory sections to determine whether any one of said polled memory sections currently requires access to any one of said computers, said memory polling means being asynchronously operated with respect to said computer polling means, memory gating means responsive to a determination that one of said memory sections currently requires access to one of said computers for gating information including said one computer identity code from said one memory section onto a second set of said buses for transmission to said one computer, and means effective upon the transmission of said identity code to said one computer for transmitting information over said second set of said buses between said one computer and said one memory section.

Claim 8

A multiprocessing system comprising: a plurality of computers, a plurality of memory sections, a plurality of time multiplexed buses interconnecting said computers with said memory sections, computer polling means for repetitively and sequentially polling said computers to determine whether any one of said polled computers currently requires access to any one of said memory sections, computer gating means responsive to a determination that one of said polled computers currently requires access to one of said memory sections for gating service request information from said one computer onto a first set of said buses for transmission to said one memory section, said service request information including the identity codes of said one computer and said one memory section, means in said one memory section for storing said transmitted information except for said one memory section identity code, memory polling means for repetitively and sequentially polling said memory sections to determine whether any one of said polled memory sections currently requires access to any one of said computers, said memory polling means being asynchronously operated with respect to said computer polling means, memory gating means responsive to a determination that one of said memory sections currently requires access to one of said computers for gating information including said one computer identity code from said one memory section onto a second set of said buses for transmission to said one computer, and means effective upon the transmission of said identity code to said one computer for transmitting information over said second set of said buses between said one computer and said one memory section.

Claim 9

The system of claim 6 wherein said computer polling means comprises: a means for generating computer timing pulses, means responsive to the generation of said computer timing pulses for repetitively interrogating said computers sequentially one at a time, and means for enabling said computer gating means when an interrogated computer requires access to one of said memory sections.

Claim 10

The system of claim 7 wherein said memory polling means comprises: a means for generating memory timing pulses, means responsive to the generation of said memory timing pulses for repetitively interrogating said memory sections sequentially one at a time, and means for enabling said memory gating means when an interrogated memory requires access to one of said computers.

Claim 11

The system of claim 8 wherein said means for interrogating said computers comprises: means responsive to said computer timing pulses for repetitively generating a sequence of different identity codes each of which is unique to a different one of said computers, means for applying each generated code to all of said computers, and means in each of said computers responsive to the receipt of its identity code for activating its gating means.

Claim 12

The system of claim 9 wherein said means for interrogating said memory sections comprises: means responsive to said memory timing pulses means for repetitively generating a sequence of different identity codes each of which is unique to a different one of said memory sections, means for applying each generated memory section identity code to all of said memory sections, and means in each of said memory sections responsive to the receipt of its identity code for activating its gating means.

Claim 13

A multiprocessing system comprising: a plurality of computers, a plurality of memory sections, a time multiplexed bus system comprising a plurality of buses interconnecting each of said computers with each of said memory sections, means for repetitively and sequentially polling said computers to determine whether any one of said polled computers currently requires access to one of said memory sections, means including gating means in each computer responsive to a determination that one of said polled computers currently requires access to one of said memory sections for connecting said one polled computer over a first set of said buses to said one memory section, means effective upon said connection for transmitting the identity code of said one memory section and service request information from said polled computer to said one memory section for storage therein, said service request information including the identity code of said one polled computer as well as a read or write request signal and memory address information, means for repetitively and sequentially polling said memory sections to determine whether any one of said polled memory sections currently requires access to one of said computers, said memory polling means and said computer polling means being asynchronously operated with respect to each other, means in each memory section including a memory gating means responsive to the polling of a memory section that currently requires access to one of said computers for connecting said polled memory section over a second set of said buses to said one computer, means responsive to said last named connection for transmitting the identity code of said one computer from said polled memory section to said one computer over said second set of buses, and means effective upon said last named connection of said polled named memory section for transmitting information over said second set of buses between said polled memory section and said one computer.

Claim 14

A multiprocessing system comprising: a plurality of computers, a plurality of memory sections, a time multiplexed bus system comprising a plurality of buses interconnecting each of said computers with each of said memory sections, means for repetitively and sequentially polling said computers to determine whether any one of said polled computers currently requires access to one of said memory sections, means including gating means in each computer responsive to a determination that one of said polled computers currently requires access to one of said memory sections for connecting said one polled computer over a first set of said buses to said one memory section, means effective upon said connection for transmitting the identity code of said one memory section and service request information from said polled computer to said one memory section for storage therein, said service request information including the identity code of said one polled computer as well as a read or write request signal and memory address information, means for repetitively and sequentially polling said memory sections to determine whether any one of said polled memory sections currently requires access to one of said computers, said memory polling means and said computer polling means being asynchronously operated with respect to each other, means in each memory section including a memory gating means responsive to the polling of a memory section that currently requires access to one of said computers for connecting said polled memory section over a second set of said buses to said one computer, means responsive to said last named connection for transmitting the identity code of said one computer from said polled memory section to said one computer over said second set of buses, and means effective upon said last named connection of said polled named memory section for transmitting information over said second set of buses between said polled memory section and said one computer.

Claim 15

The system of claim 11 wherein said computer polling means comprises: means for generating computer timing pulses, means responsive to the generation of said timing pulses for generating coded computer interrogation pulses, means for applying said interrogation pulses to said computers to repetitively interrogate said computers sequentially one at a time, and means for enabling said computer gating means for the duration of an interrogation pulse when an interrogated computer requires access to a memory section.

Claim 16

The system of claim 12 wherein said means for generating coded computer interrogation pulses comprises: means responsive to said computer timing pulses for repetitively generating a sequence of different identity codes with each code being unique to a different one of said computers, means for applying each generated code to all of said computers, means in each of said computers responsive to the receipt of its identity code for activating its gating means for the duration of the receipt of its coded interrogation pulse, means responsive to the interrogation of a computer that requires access to one of said memory sections for transmitting a service request signal to said computer polling means, and means responsive to said service request signal for increasing the time duration of the interrogation pulses applied to said interrogated computer.

Claim 17

The system of claim 13 wherein said memory polling means comprises: means for generating memory timing pulses, means responsive to the generation of said memory timing pulses for generating coded memory interrogation pulses, means for applying said memory interrogation pulses to said memory sections for repetitively interrogating said memory sections sequentially one at a time, and means for enabling said memory gating means for the duration of an interrogation pulse.

Claim 18

The system of claim 14 wherein said means for generating memory interrogation pulses comprises: means responsive to said memory timing pulses for repetitively generating a sequence of different identity codes with each code being unique to a different one of said memory sections, means for applying each generated memory identity code to all of said memory sections, means in each of said memory sections responsive to the receipt of its identity code for activating its gating means for the duration of the receipt of its coded interrogation pulses, and means responsive to the interrogation of a memory section for transmitting information over said bus system to one of said computers.

Claim 19

In a multiprocessor system having a plurality of computers, a memory having interleaved sections, a plurality of time multiplexed buses interconnecting said computers with said memory sections, each of said buses being common to all of said computers and all of said memory sections, a first clock for generating computer timing pulses, means controlled by said computer timing pulses for repetitively and sequentially polling each of said computers one at a time to determine whether any one of said polled computers currently requires access to any one of said memory sections, computer gating means responsive to a determination that one of said computers requires access to one of said memory sections for gating service request information including the identity code of said one memory section to a first set of said buses, said service request information further including the identity code of said one polled computer as well as a read or write request signal and memory address information, means in said one memory section responsive to the appearance of its identity code on said first set of buses for registering the remainder of said service request information transmitted from said one polled computer, a second clock asynchronously operated from said first clock for generating memory timing pulses, means controlled by said memory timing pulses for repetitively and sequentially polling each of said memory sections one at a time, means responsive to the polling of a memory section having registered service request information from one of said computers for applying information including the identity code of said one computer to a second set of said buses, and means responsive to the appearance of said one computer identity code on said second set of buses for transmitting information between said one computer and said polled memory section.

Claim 20

In a multiprocessor system having a plurality of computers, a memory having interleaved sections, a plurality of time multiplexed buses interconnecting said computers with said memory sections, each of said buses being common to all of said computers and all of said memory sections, a first clock for generating computer timing pulses, means controlled by said computer timing pulses for repetitively and sequentially polling each of said computers one at a time to determine whether any one of said polled computers currently requires access to any one of said memory sections, computer gating means responsive to a determination that one of said computers requires access to one of said memory sections for gating service request information including the identity code of said one memory section to a first set of said buses, said service request information further including the identity code of said one polled computer as well as a read or write request signal and memory address information, means in said one memory section responsive to the appearance of its identity code on said first set of buses for registering the remainder of said service request information transmitted from said one polled computer, a second clock asynchronously operated from said first clock for generating memory timing pulses, means controlled by said memory timing pulses for repetitively and sequentially polling each of said memory sections one at a time, means responsive to the polling of a memory section having registered service request information from one of said computers for applying information including the identity code of said one computer to a second set of said buses, and means responsive to the appearance of said one computer identity code on said second set of buses for transmitting information between said one computer and said polled memory section.

Claim 21

The system of claim 16 in which said means for polling said computers further comprises: means responsive to the polling of a computer that requires access to one of said memory sections for applying a set of long duration control pulses to said polled computer, means responsive to said long duration control pulses for controlling the transmission of said service request information from said polled computer to said one memory section, and means responsive to the polling of a computer that does not require access to one of said memory sections for applying a set of short duration control pulses to said polled computer.

Claim 22

The system of claim 17 in which said computer polling means sequentially polls each of said computers in a first recurring time interval, and in which said memory polling means sequentially polls each of said sections in a second recurring time interval that a asynchronous from said first time interval.

Claim 23

In a multiprocessor system having a plurality of computers, a plurality of memory sections, a plurality of time multiplexed buses interconnecting each of said computers with each of said memory sections, means in each computer for generating a service request for access over a first set of said buses to one of said memory sections, means in each computer for registering the service request generated within the computer, computer polling means for repetitively and sequentially polling each of said computers for registered service requests one at a time, means including computer gating means responsive to the polling of a computer having a currently registered service request for applying service request information including the identity code of said one memory section and said polled computer to said first set of said buses, means in said one memory section responsive to the appearance of its identity code on said first set of buses for registering the remainder of the service request information applied to said first set of buses by said polled computer having a registered service request, memory polling means asynchronously operated with respect to said computer polling means for repetitively and sequentially polling each of said memory sections one at a time, means including memory gating means responsive to the polling of a memory section having registered service request information priorly received from one of said computers for applying information from said polled memory section to a second set of said buses with said information from said polled memory section including the identity code of said one computer that has priorly service request transmitted information to said polled memory section, and means responsive to the appearance of said one computer identity code on said second set of buses for transmitting information over said second set of said buses between said polled memory section and said one computer.

Claim 24

In a multiprocessor system having a plurality of computers, a plurality of memory sections, a plurality of time multiplexed buses interconnecting each of said computers with each of said memory sections, means in each computer for generating a service request for access over a first set of said buses to one of said memory sections, means in each computer for registering the service request generated within the computer, computer polling means for repetitively and sequentially polling each of said computers for registered service requests one at a time, means including computer gating means responsive to the polling of a computer having a currently registered service request for applying service request information including the identity code of said one memory section and said polled computer to said first set of said buses, means in said one memory section responsive to the appearance of its identity code on said first set of buses for registering the remainder of the service request information applied to said first set of buses by said polled computer having a registered service request, memory polling means asynchronously operated with respect to said computer polling means for repetitively and sequentially polling each of said memory sections one at a time, means including memory gating means responsive to the polling of a memory section having registered service request information priorly received from one of said computers for applying information from said polled memory section to a second set of said buses with said information from said polled memory section including the identity code of said one computer that has priorly service request transmitted information to said polled memory section, and means responsive to the appearance of said one computer identity code on said second set of buses for transmitting information over said second set of said buses between said polled memory section and said one computer.

Claim 25

The system of claim 19 wherein said computer control means for polling said computers comprises: means for generating computer timing pulses, means responsive to the generation of said computer timing pulses for repetitively generating a sequence of different identity codes with each code being unique to a different one of said computers, means for applying each generated code to all of said computers, and means in each of said computers having a registered service request and responsive to the receipt of its identity code for activating its gating means to connect said computer signalwise to said first set of buses for the duration of the polling of said computer.

Claim 26

The system of claim 20 wherein said memory control means for polling said memory sections comprises: means for generating memory timing pulses, means responsive to the generation of said memory timing pulses for repetitively generating a sequence of different identity codes with each code being unique to a different one of said memory sections, means for applying each generated memory identity code to all of said memory sections, and means in each of said memory sections responsive to the receipt of its identity code for activating its gating means to connect said memory section signalwise to said second bus for the duration of the receipt of the polling of said memory section.

Claim 27

The system of claim 21 in which said computer control means for polling said computers further comprises: means responsive to the polling of a computer that has a registered service request for applying a set of long duration control pulses to said polled computer, means responsive to said long duration control pulses for controlling the transmission of said information from said polled computer to said one memory section, and means responsive to the polling of a computer that does not have a registered service request for applying a set of short duration control pulses to said polled computer.

Claim 30

The method of claim 23 in which the step of polling said computers further comprises the steps of: (1) repetitively generating a sequence of different computer identity codes which each code being unique of said computers, (2) applying each generated computer identity code to all of said computers, (3) applying a set of computer control pulses of a first duration to each of said computers following the application of each computer identity code, (4) returning a service request signal to a computer controller upon the polling of a computer having a registered service request as the identity code of the polled control is applied, to the computer, and (5) increasing the duration of the control pulses applied to a polled computer upon the receipt of a service request signal from the polled computer.

Claim 31

The method of claim 23 in which said method further comprises the step of: (1) activating gating circuitry within a polled computer having a service request for controlling the application of said information from said polled computer to the said first bus during the polling duration.

Claim 32

The method of claim 23 in which the step of polling the memory sections comprises the steps of: (1) generating control pulses including memory section identity codes with each code being unique to a different said memory section, (2) applying each generated memory section code to all of said memory sections, and (3) activating gating circuitry in each polled memory section upon the receipt of its identity code for controlling the application of information from the polled memory section to the second bus.