Method of and arrangement for the distribution of timing pulses in an electronic data processor

Claim 1

A system for the distribution of timing pulses in a data processing system having a plurality of processing units connected to each other and at least one memory along lines in both the data pulse bus and timing pulse bus networks, comprising: a timing pulse generator means; control gate pair means for coupling the timing pulse generator means to the individual lines of the timing pulse bus network with one control gate in each gate pair linking one end of a line of the timing pulse bus network to the timing pulse generator and the other gate in that pair linking the other end of the same line to the timing pulse generator; latch circuit means coupled to said gate pair means to provide a gating signal to only one gate in each pair to open the gate to timing pulses from the timing pulse generator; and transmission control means for controlling the production of the gating signal by the latch circuit means in response to the direction of transmission of the data signals on the data bus and causing the latch means to provide a signal to the gates in the gate pair that permits transmission of timing signals along the timing pulse bus network in the same direction as the data is being transmitted along the data pulse bus network.

Claim 2

A system for the distribution of timing pulses in a data processing system having a plurality of processing units connected to each other and at least one memory along lines in both the data pulse bus and timing pulse bus networks, comprising: a timing pulse generator means; control gate pair means for coupling the timing pulse generator means to the individual lines of the timing pulse bus network with one control gate in each gate pair linking one end of a line of the timing pulse bus network to the timing pulse generator and the other gate in that pair linking the other end of the same line to the timing pulse generator; latch circuit means coupled to said gate pair means to provide a gating signal to only one gate in each pair to open the gate to timing pulses from the timing pulse generator; and transmission control means for controlling the production of the gating signal by the latch circuit means in response to the direction of transmission of the data signals on the data bus and causing the latch means to provide a signal to the gates in the gate pair that permits transmission of timing signals along the timing pulse bus network in the same direction as the data is being transmitted along the data pulse bus network.