Patent US3981440A successfully refreshed from Google Patents.
US3981440A
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Digital signal detector
Assignee: International Telephone and Telegraph Corp
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Filing: 1974-09-25
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Granted: 1976-09-21
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Expires: 1994-09-25
Abstract
Abstract An apparatus is provided for detecting digital pulses or pulse intervals and any combination thereof. Logic means is provided wherein the complement of the interval to be measured is loaded into a digital counter, and certain states of this counter are decoded to set and reset, respectively, an in-bin flip-flop. Operation is initiated when a digital input is received. If the interval to be measured terminates while the in-bin flip-flop is set, an output is generated indicating that a "hit" has been scored and the parameters of the measurement can be read out. Code words stored in a memory provide the specific parameters of measurement, and particular portions of the code words are employed depending on the desired mode of operation. Each code word contains data corresponding to the interval to be measured, desired resolution, clock rate to be employed, end of cycle in cases where a pattern of pulses and intervals is to be detected, and an indication of whether a pulse or an interval between pulses is to be measured.
Inventors
- 👤 Alexander Laidlaw Richardson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 19:35
CPC Classifications
G; G01; G01S; G01S1/00; G01S1/02; G01S1/04; G01R; G01R29/00; G01R29/02; G01S13/00; G01S13/74; G01S13/76; G01S13/78; G01S13/781; G01S13/784; G04; G04F; G04F10/00; G04F10/04
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
174 words
An apparatus for recognizing a plurality of digital signals having different pulse widths or pulse repetition intervals comprising: a presettable digital counter; a memory containing a plurality of binary code words, which code words contain the binary complement of the interval to be measured, said memory coupled to said presettable counter for loading said complement into said presettable counter; means for receiving digital input signals to be measured, said digital signals including pulses and intervals between pulses; pulse interval converter means coupled to said receiving means, said memory, and said presettable counter for inverting said digital input signal when a current code word indicates that an interval between pulses is to be measured; logic means coupled to said presettable counter for generating a signal corresponding to an acceptable time interval within which a desired input interval must end; means coupled to means for receiving for indicating when an input interval has terminated; means for generating an ouput when said indication occurs during said acceptable time interval; and means for varying said acceptable time interval.
Claim 2
Independent Claim
174 words
An apparatus for recognizing a plurality of digital signals having different pulse widths or pulse repetition intervals comprising: a presettable digital counter; a memory containing a plurality of binary code words, which code words contain the binary complement of the interval to be measured, said memory coupled to said presettable counter for loading said complement into said presettable counter; means for receiving digital input signals to be measured, said digital signals including pulses and intervals between pulses; pulse interval converter means coupled to said receiving means, said memory, and said presettable counter for inverting said digital input signal when a current code word indicates that an interval between pulses is to be measured; logic means coupled to said presettable counter for generating a signal corresponding to an acceptable time interval within which a desired input interval must end; means coupled to means for receiving for indicating when an input interval has terminated; means for generating an ouput when said indication occurs during said acceptable time interval; and means for varying said acceptable time interval.
Claim 3
Dependent Claim
24 words
An apparatus according to claim 1 further including a variable clock pulse generator for controlling the rate at which said presettable counter will count.
Claim 4
Dependent Claim
72 words
An apparatus according to claim 2 wherein said logic means comprises: a flip-flop; first means coupled to said presettable counter and to said flip-flop for detecting a first state of said counter and setting said flip-flop; and second means coupled to said presettable counter and to said flip-flop for resetting said flip-flop when said presettable counter has reached a full count, the output of said flip-flop corresponding to said acceptable time interval.
Claim 5
Dependent Claim
25 words
An apparatus according to claim 3 wherein said digital code words contain binary information for controlling said variable clock pulse generator and said first means.
Claim 6
Dependent Claim
25 words
An apparatus according to claim 4 wherein said code word contains an indication that the last pulse of a particular pulse pattern has been received.
Claim 7
Dependent Claim
34 words
An apparatus according to claim 5 further including a control counter, coupled to said generating means; and means coupled to said control counter and to said generating means for selecting a specific code word.
References Cited (Backward Citations)
US3581066A
Cited
US3714645A
Cited
US3667054A
Cited
US3728635A
Cited
US3790881A
Cited
US3840174A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-09-21 | 1980-03-22 | 1980-09-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-09-21 | 1984-03-22 | 1984-09-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-09-21 | 1988-03-22 | 1988-09-21 | $7700.00 | Window Closed / Lapsed |