Pulsed selectable delay system

Claim 2

Apparatus for generating output signal pulses which are identical to but delayed in time from input signal pulses, said apparatus comprising a first counter, means for loading said first counter with a digital word representing the time interval that the pulse generation is to be delayed, a second counter, a source of clock pulses applied to said first and second counters to be counted thereby, means for applying input signal pulses to said first and second counters to cause said counters to count clock pulses from said source, said first counter generating an output signal when it counts to its limit, said second counter counting clock pulses so long as an input signal pulse exits, means connected to the output of said first counter for initiating the generation of an output signal pulse when said first counter generates an output signal, means for connecting said second counter to the output of said first counter to cause said second counter to count clock pulses from said source in an opposite manner when said first counter generates an output signal, and means for terminating the generation of said output signal pulse when said second counter reaches zero.

Claim 3

Apparatus for generating output signal pulses, which are identical to but selectively delayed from input signal pulses, said apparatus comprising a delay counter, a source of timing pulses, means for inserting into said delay counter a digital word representative of the selected delay, means for applying to the count input of said delay counter timing pulses to be counted from the value of the inserted word, means for inhibiting said delay counter from counting, means for applying input signal pulses to said inhibiting means for causing said delay counter to count timing pulses when an input signal pulse is present, means connected to the output of said delay counter to initiate the generation of an output signal pulse when said counter produces an output signal, a pulse width counter, means for connecting the count input of the pulse width counter to said source of timing pulses, means connected to said pulse width counter and responsive to an input signal pulse to cause said pulse width counter to count timing pulses so long as an input signal pulse is present, means responsive to the production of an output signal by said delay counter for causing said pulse width counter to count in the opposite direction, and means responsive to a zero count in said pulse width counter for terminating the generation of an output signal pulse.

Claim 4

Apparatus for generating output signal pulses, which are identical to but selectively delayed from input signal pulses, said apparatus comprising a delay counter, a source of timing pulses, means for inserting into said delay counter a digital word representative of the selected delay, means for applying to the count input of said delay counter timing pulses to be counted from the value of the inserted word, means for inhibiting said delay counter from counting, means for applying input signal pulses to said inhibiting means for causing said delay counter to count timing pulses when an input signal pulse is present, means connected to the output of said delay counter to initiate the generation of an output signal pulse when said counter produces an output signal, a pulse width counter, means for connecting the count input of the pulse width counter to said source of timing pulses, means connected to said pulse width counter and responsive to an input signal pulse to cause said pulse width counter to count timing pulses so long as an input signal pulse is present, means responsive to the production of an output signal by said delay counter for causing said pulse width counter to count in the opposite direction, and means responsive to a zero count in said pulse width counter for terminating the generation of an output signal pulse.

Claim 5

The apparatus defined in claim 3 further including means reSponsive to the production of an output signal by said interval counter to halt the counting of timing pulses by said pulse width counter whereby said pulse width counter is halted by the occurance of the first of the termination of an input signal pulse or by an output signal from said interval counter.

Claim 6

Apparatus for generating duplicate signal pulses from input signal samples at selected time intervals, said apparatus comprising means for receiving a sample input signal pulse, a first counter, a source of clock pulses, means for inserting into said first counter a number whose value is representative of a time interval, means for applying an input signal pulse from said receiving means to said first counter to initiate the counting of clock pulses by said counter until the capacity of said counter is reached, said counter generating an output signal when its capacity is reached, means responsive to the generation of a counter output signal for terminating further counting by said counter, means responsive to the output from said first counter for generating an output signal pulse, means for determining the width of the output signal pulse, said width determining means comprising a width counter, means for supplying clock pulses to be counted by said width counter while said signal pulse is applied to said receiving means, means for interrupting the operation of said width counter when the signal pulse is no longer present at said receiving means, means for initiating the operation of said width counter in the opposite direction when said interval counter produces an output signal, and means for terminating the generation of said output signal pulse when said width counter reaches a zero value.

Claim 7

Apparatus for generating duplicate signal pulses from input signal samples at selected time intervals, said apparatus comprising means for receiving a sample input signal pulse, a first counter, a source of clock pulses, means for inserting into said first counter a number whose value is representative of a time interval, means for applying an input signal pulse from said receiving means to said first counter to initiate the counting of clock pulses by said counter until the capacity of said counter is reached, said counter generating an output signal when its capacity is reached, means responsive to the generation of a counter output signal for terminating further counting by said counter, means responsive to the output from said first counter for generating an output signal pulse, means for determining the width of the output signal pulse, said width determining means comprising a width counter, means for supplying clock pulses to be counted by said width counter while said signal pulse is applied to said receiving means, means for interrupting the operation of said width counter when the signal pulse is no longer present at said receiving means, means for initiating the operation of said width counter in the opposite direction when said interval counter produces an output signal, and means for terminating the generation of said output signal pulse when said width counter reaches a zero value.