Encoding scheme for failure detection in random access memories

Claim 3

A method as set forth in claim 1 wherein said step of generating a first check code field further comprises the steps of - a. determining the sum of the total number of binary ones in said data field; b. representing said sum as a binary number; c. and complementing, bit by bit, said binary number.

Claim 4

A method as set forth in claim 1 wherein said step of generating a second check code field further comprises the steps of - a. determining the sum of the total number of binary ones in the binary representation of said address; b. representing said sum as a binary number; c. and complementing, bit by bit, said binary number.

Claim 5

A method as set forth in claim 1 wherein said step of generating an error indication further comprises the steps of - a. generating a first error signal whenever said first stored code field is not identical to said first check code field; b. and generating a second error signal whenever said second stored code field is not identical to said second check code field.

Claim 6

A combination for detecting and indicating errors in an information storage system comprising; memory means including a plurality of addressable words, information handling means, memory accessing and registering means, connected to said information handling means and to said memory means, operative to extract and register a word stored in said memory means corresponding to an address provided by said information handling means, first encoder means, connected to and receiving inputs from said accessing and registering means, operative to generate a first check code field suitable for use in detecting all multiple unidirectional errors in a first predetermined portion of an extracted word, second encoder means, connected to and receiving inputs from said memory accessing and registering means, operative to generate a second check code field suitable for use in detecting at least a single error in the address of said extracted word, a first comparator, connected to and receiving inputs from both said memory accessing and registering means and said first encoder means, operative to generate a first error signal whenever said first check code field is not identical to a second predetermined portion of said extracted word, a second comparator, connected to and receiving inputs from both said memory accessing and registering means and said second encoder means, operative to generate a second error signal whenever said second check code field is not identical to a third predetermined portion of said extracted word, and said information handling means further including means, connected to both said first and second comparators, for processing said first and second error signals, whenever present, to indicate the occurrence of a storage system error.

Claim 7

A combination for detecting and indicating errors in an information storage system comprising; memory means including a plurality of addressable words, information handling means, memory accessing and registering means, connected to said information handling means and to said memory means, operative to extract and register a word stored in said memory means corresponding to an address provided by said information handling means, first encoder means, connected to and receiving inputs from said accessing and registering means, operative to generate a first check code field suitable for use in detecting all multiple unidirectional errors in a first predetermined portion of an extracted word, second encoder means, connected to and receiving inputs from said memory accessing and registering means, operative to generate a second check code field suitable for use in detecting at least a single error in the address of said extracted word, a first comparator, connected to and receiving inputs from both said memory accessing and registering means and said first encoder means, operative to generate a first error signal whenever said first check code field is not identical to a second predetermined portion of said extracted word, a second comparator, connected to and receiving inputs from both said memory accessing and registering means and said second encoder means, operative to generate a second error signal whenever said second check code field is not identical to a third predetermined portion of said extracted word, and said information handling means further including means, connected to both said first and second comparators, for processing said first and second error signals, whenever present, to indicate the occurrence of a storage system error.

Claim 8

A combinaton as set forth in claim 5 wherein said first check code field comprises a sum code.

Claim 9

A combination as set forth in claim 5 wherein said second check code field comprises a sum code.

Claim 10

A combination as set forth in claim 5 wherein said second check code field comprises a code suitable for use in detecting single random errors in said address provided by said information handling means.

Claim 11

A combination as set forth in claim 5 wherein said memory means further comprises; a first memory module for storing said first predetermined portion of said words, and a second memory module for storing said second and said third predetermined portions of said words.

Claim 12

A combination as set forth in claim 5 wherein said first encoder means further comprises; a word-organized read-only memory, accessing means, connected to said read-only memory, for utilizing the inputs to said first encoder means as the address of a word in said read-only memory, and output means, connected to said read-only memory, to permit the contents of the read-only memory word so addressed to be output from said read-only memory to the outputs of said first encoder means.

Claim 13

A combination as set forth in claim 5 wherein said second encoder means further comprises; a word-organized read-only memory, accessing means, connected to said read-only memory, for utilizing the inputs to said second encoder means as the address of a word in said read-only memory, and output means, connected to said read-only memory, to permit the contents of the read-only memory word so addressed to be output from said read-only memory to the outputs of said second encoder means.

Claim 14

A combination as set forth in claim 5 wherein said second encoder means further comprises; parity check generator means, with inputs connected to said memory accessing and registering means, operative to produce a single parity check bit in response to the binary address information received over said inputs from said memory accessing and registering means, and means for transmitting said single parity check bit to the output of said second encoder means.

Claim 17

A combination for detecting and indicating errors in an information storage system comprising; memory means including a plurality of addressable words, information handling means, memory accessing and registering means, connected to said information handling means and to said memory means, operative to extract and register a word stored in said memory means corresponding to an address provided by said information handling means, first encoder means, connected to and receiving inputs from said accessing and registering means, operative to generate a first check code field suitable for use in detecting all multiple unidirectional errors in a first predetermined portion of an extracted word, second encoder means, connected to and receiving inputs from said memory accessing and registering means, operative to generate a second check code field suitable for use in detecting at least a single error in the address of said extracted word, a first comparison means, connected to and receiving inputs from both said memory accessing and registering means and said first encoder means, operative to generate a first error signal whenever said first check code field does not exhibit a predetermined relationship to a second predetermined portion of said extracted word, a second comparison means, connected to and receiving inputs from both said memory accessing and registering means and said second encoder means, operative to generate a second error signal whenever said second check code field does not exhibit a predetermined relationship to a third predetermined portion of said extracted word, and said information handling means further including means, connected to both said first and second comparison means, for processing said first and second error signals, whenever present, to indicate the occurrence of a storage system error.

Claim 18

A combination for detecting and indicating errors in an information storage system comprising; memory means including a plurality of addressable words, information handling means, memory accessing and registering means, connected to said information handling means and to said memory means, operative to extract and register a word stored in said memory means corresponding to an address provided by said information handling means, first encoder means, connected to and receiving inputs from said accessing and registering means, operative to generate a first check code field suitable for use in detecting all multiple unidirectional errors in a first predetermined portion of an extracted word, second encoder means, connected to and receiving inputs from said memory accessing and registering means, operative to generate a second check code field suitable for use in detecting at least a single error in the address of said extracted word, a first comparison means, connected to and receiving inputs from both said memory accessing and registering means and said first encoder means, operative to generate a first error signal whenever said first check code field does not exhibit a predetermined relationship to a second predetermined portion of said extracted word, a second comparison means, connected to and receiving inputs from both said memory accessing and registering means and said second encoder means, operative to generate a second error signal whenever said second check code field does not exhibit a predetermined relationship to a third predetermined portion of said extracted word, and said information handling means further including means, connected to both said first and second comparison means, for processing said first and second error signals, whenever present, to indicate the occurrence of a storage system error.