Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
320 words
In a testing apparatus for detecting faults in a semiconductor memory array made up of a plurality of memory cells, each cell being capable of storing a binary bit of information, each cell being addressed by an X-address signal and a Y-address signal, said testing apparatus including: a. program means for generating a testing signal; b. X-counter means, controlled by said program means, for generating an X-address signal for the semiconductor memory array to be tested; c. Y-counter means, controlled by said program means, for generating a Y-address signal for the semiconductor memory array to be tested; d. judging means, coupled to said semiconductor memory array to be tested, for generating judgment signals representative of the results of the testing of a respective cell within said semiconductor memory array, addressed by said X-counter means and said Y-counter means; e. memory means, coupled to said judging means, for storing judgement signals representative of the results of the testing of a respective cell; and f. first gate means connected between said judging means and said memory means, for controllably coupling said judgment signals to said memory means; the improvement comprising; g. mask appointment means for generating a masking signal representative of the address of a memory cell known to be defective; h. signal generating means, coupled to said X-counter means, said Y-counter means, and said mask appointment means, for comparing said masking signal with the X-address signals and Y-address signals by which the memory cells of the semiconductor memory array are addressed during the testing thereof, and for generating a mask signal upon coincidence of the masking signal with said X-address and Y-address signals; and i. second gate means, coupled between said signal generating means and said first gate means, and receiving a timing pulse, for inhibiting the transmission of said timing pulse to said first gate means, in response to the generation of a mask signal by said signal generating means.
Claim 2
Dependent Claim
320 words
In a testing apparatus for detecting faults in a semiconductor memory array made up of a plurality of memory cells, each cell being capable of storing a binary bit of information, each cell being addressed by an X-address signal and a Y-address signal, said testing apparatus including: a. program means for generating a testing signal; b. X-counter means, controlled by said program means, for generating an X-address signal for the semiconductor memory array to be tested; c. Y-counter means, controlled by said program means, for generating a Y-address signal for the semiconductor memory array to be tested; d. judging means, coupled to said semiconductor memory array to be tested, for generating judgment signals representative of the results of the testing of a respective cell within said semiconductor memory array, addressed by said X-counter means and said Y-counter means; e. memory means, coupled to said judging means, for storing judgement signals representative of the results of the testing of a respective cell; and f. first gate means connected between said judging means and said memory means, for controllably coupling said judgment signals to said memory means; the improvement comprising; g. mask appointment means for generating a masking signal representative of the address of a memory cell known to be defective; h. signal generating means, coupled to said X-counter means, said Y-counter means, and said mask appointment means, for comparing said masking signal with the X-address signals and Y-address signals by which the memory cells of the semiconductor memory array are addressed during the testing thereof, and for generating a mask signal upon coincidence of the masking signal with said X-address and Y-address signals; and i. second gate means, coupled between said signal generating means and said first gate means, and receiving a timing pulse, for inhibiting the transmission of said timing pulse to said first gate means, in response to the generation of a mask signal by said signal generating means.
Claim 3
Dependent Claim
20 words
The improvement according to claim 1, wherein each of said first and second gate means comprises a respective AND gate.