Method for fabricating and assembling a block-addressable semiconductor mass memory

Claim 1

A method for fabricating and assembling an integrated-circuit store of the type comprising a plurality of arrays, each array storing a block of data and including an address recognizing means, said method comprising the steps of: A. photographically forming from a corresponding set of master masks of an array a set of masks for manufacturing integrated circuits, the set of master masks including a bus-portion image, wherein the step of forming the set of master masks includes the step of repeatedly aligning and abutting the busportion image to form an image of an input-output bus; B. forming a group of arrays on a wafer utilizing the set of masks formed in the preceding step, the group of arrays electrically interconnected by the input-output bus; C. enabling one of the arrays to the input-output bus; D. testing the one array for operability; E. storing an address in the address recognizing means of the tested operable array; and F. connecting the tested operable array to the input-output bus.

Claim 2

A method for fabricating and assembling an integrated-circuit store of the type comprising a plurality of arrays, each array storing a block of data and including an address recognizing means, said method comprising the steps of: A. photographically forming from a corresponding set of master masks of an array a set of masks for manufacturing integrated circuits, the set of master masks including a bus-portion image, wherein the step of forming the set of master masks includes the step of repeatedly aligning and abutting the busportion image to form an image of an input-output bus; B. forming a group of arrays on a wafer utilizing the set of masks formed in the preceding step, the group of arrays electrically interconnected by the input-output bus; C. enabling one of the arrays to the input-output bus; D. testing the one array for operability; E. storing an address in the address recognizing means of the tested operable array; and F. connecting the tested operable array to the input-output bus.

Claim 6

A method for fabricating and assembling an integrated-circuit store of the type comprising a plurality of basic circuits, each basic circuit storing a block of data and including an address recognizing means, said method comprising the steps of: A. photographically forming from a corresponding set of master masks of a basic circuit a set of wafer-size masks for manufacturing integrated circuits, the set of master masks including a bus-portion image, wherein the step of forming the set of wafer-size masks includes the step of repeatedly aligning and abutting the bus-portion image to form an input-Output bus image; B. forming on a wafer of semiconductor material a group of basic circuits utilizing the set of wafer-size masks formed in the preceding step, the group of basic circuits including an input-output bus electrically interconnecting the group of basic circuits each to the other; C. enabling one of the basic circuits to the input-output bus; D. applying address signals to the input-output bus; E. applying clock signals, control signals and data signals to the input-output bus; F. testing the one basic circuit for operability in response to the applied signals; G. storing an address in the address recognizing means of the tested operable basic circuit; and H. applying a connect voltage to the tested basic circuit to connect the tested basic circuit to the input-output bus.

Claim 7

A method for fabricating and assembling an integrated-circuit store of the type comprising a plurality of basic circuits, each basic circuit storing a block of data and including an address recognizing means, said method comprising the steps of: A. photographically forming from a corresponding set of master masks of a basic circuit a set of wafer-size masks for manufacturing integrated circuits, the set of master masks including a bus-portion image, wherein the step of forming the set of wafer-size masks includes the step of repeatedly aligning and abutting the bus-portion image to form an input-Output bus image; B. forming on a wafer of semiconductor material a group of basic circuits utilizing the set of wafer-size masks formed in the preceding step, the group of basic circuits including an input-output bus electrically interconnecting the group of basic circuits each to the other; C. enabling one of the basic circuits to the input-output bus; D. applying address signals to the input-output bus; E. applying clock signals, control signals and data signals to the input-output bus; F. testing the one basic circuit for operability in response to the applied signals; G. storing an address in the address recognizing means of the tested operable basic circuit; and H. applying a connect voltage to the tested basic circuit to connect the tested basic circuit to the input-output bus.

Claim 8

A method for fabricating and assembling a semi-conductor memory of the type comprising a plurality of identical basic circuits, each of the basic circuits storing a block of data and each including an address identifying means, said method comprising the steps of: A. photographically forming from a corresponding set of master masks of a basic circuit a set of wafer-size masks for manufacturing integrated circuits, the set of master masks including a bus-portion image, wherein the step of forming the set of wafer-size masks includes the step of repeatedly aligning and abutting the bus-portion image to form a wafer-size input-output bus image; B. forming on a wafer of semiconductor material a group of identical basic circuits utilizing the set of wafer-size masks formed in the preceding step, the group of basic circuits including an input-output bus electrically interconnecting the group of basic circuits; C. temporarily enabling one of the basic circuits to the input-output bus; D. testing the temporarily enabled basic circuit for operability; E. disabling the temporarily enabled basic circuit from the input-output bus if the basic circuit is found defective during the testing step and proceeding to step H, otherwise proceeding to step F; F. storing a unique address in the address identifying means in the temporarily enabled basic circuit determined operable during the testing step; G. connecting the operable addressable basic circuit to the input-output bus; and H. repeating steps C, D and E for successive ones of the basic circuits on the wafer until a desired number of operable and uniquely addressable basic circuits on the wafer are enabled to the input-output bus.

Claim 9

A method for fabricating and assembling a semi-conductor memory of the type comprising a plurality of identical basic circuits, each of the basic circuits storing a block of data and each including an address identifying means, said method comprising the steps of: A. photographically forming from a corresponding set of master masks of a basic circuit a set of wafer-size masks for manufacturing integrated circuits, the set of master masks including a bus-portion image, wherein the step of forming the set of wafer-size masks includes the step of repeatedly aligning and abutting the bus-portion image to form a wafer-size input-output bus image; B. forming on a wafer of semiconductor material a group of identical basic circuits utilizing the set of wafer-size masks formed in the preceding step, the group of basic circuits including an input-output bus electrically interconnecting the group of basic circuits; C. temporarily enabling one of the basic circuits to the input-output bus; D. testing the temporarily enabled basic circuit for operability; E. disabling the temporarily enabled basic circuit from the input-output bus if the basic circuit is found defective during the testing step and proceeding to step H, otherwise proceeding to step F; F. storing a unique address in the address identifying means in the temporarily enabled basic circuit determined operable during the testing step; G. connecting the operable addressable basic circuit to the input-output bus; and H. repeating steps C, D and E for successive ones of the basic circuits on the wafer until a desired number of operable and uniquely addressable basic circuits on the wafer are enabled to the input-output bus.

Claim 11

A method for fabricating and assembling an integrated circuit store of the type comprising a plurality of identical basic circuits, each of the basic circuits storing a block of data and including an address-identifying means, said method comprising the steps of: A. photographically forming from a corresponding set of master masks of a basic circuit a set of wafer-size masks for manufacturing integrated circuits, the set of master masks including a bus-portion image, wherein the step of forming the set of wafer-size masks includes the step of repeateDly aligning and abutting the bus-portion image to form an input-output bus image; B. forming on a wafer of semiconductor material a group of basic circuits utilizing the set of wafer-size masks formed in the preceding step, the group of basic circuits including an input-output bus electrically interconnecting the group of basic circuits; C. enabling one of the basic circuits to the input-output bus; D. applying predetermined address signals to the group of basic circuits via the input-output bus; E. applying clock signals and control signals to the input-output bus; F. testing the one basic circuit for operability in response to the applied signals by writing data into and reading data from the one basic circuit; G. storing a unique address in the address identifying means of the tested operable basic circuit; H. applying a connect voltage to the operable basic circuit to connect the circuit to the input-output bus; and I. repeating steps C through H for successive ones of the basic circuits until a desired number of operable basic circuits are enabled to the input-output bus.

Claim 12

A method for fabricating and assembling an integrated circuit store of the type comprising a plurality of identical basic circuits, each of the basic circuits storing a block of data and including an address-identifying means, said method comprising the steps of: A. photographically forming from a corresponding set of master masks of a basic circuit a set of wafer-size masks for manufacturing integrated circuits, the set of master masks including a bus-portion image, wherein the step of forming the set of wafer-size masks includes the step of repeateDly aligning and abutting the bus-portion image to form an input-output bus image; B. forming on a wafer of semiconductor material a group of basic circuits utilizing the set of wafer-size masks formed in the preceding step, the group of basic circuits including an input-output bus electrically interconnecting the group of basic circuits; C. enabling one of the basic circuits to the input-output bus; D. applying predetermined address signals to the group of basic circuits via the input-output bus; E. applying clock signals and control signals to the input-output bus; F. testing the one basic circuit for operability in response to the applied signals by writing data into and reading data from the one basic circuit; G. storing a unique address in the address identifying means of the tested operable basic circuit; H. applying a connect voltage to the operable basic circuit to connect the circuit to the input-output bus; and I. repeating steps C through H for successive ones of the basic circuits until a desired number of operable basic circuits are enabled to the input-output bus.

Claim 13

A method for fabricating and assembling a block-addressable integrated-circuit store having n address lines and comprising a plurality of basic circuits, each of the basic circuits storing a block of data and including an address identifying means, said method comprising the steps of: A. photographically forming from a corresponding set of master masks of a basic circuit a set of wafer-size masks for manufacturing integrated circuits, the set of master masks including a bus-portion image, wherein the step of forming the wafer-size masks includes the step of repeatedly aligning and abutting the bus-portion image to form a wafer-size input-output bus image; B. forming on a wafer of semiconductor material a group of identical basic circuits including an input-output bus having said n address lines utilizing the set of wafer-size masks formed in the preceding step, the input-output bus electrically interconnecting the group of identical basic circuits each to the other; C. temporarily enabling one of the basic circuits to the input-output bus; D. testing via the input-output bus the temporarily enabled basic circuit for operability; E. disabling the temporarily enabled basic circuit from the input-output bus if the one basic circuit is found defective during the testing step and proceeding to step H, otherwise proceeding to step F; F. storing a unique address in a storage means in the temporarily enabled basic circuit determined operable during the testing step; G. connecting the operable, uniquely addressable basic circuit to the input-output bus; and H. repeating steps C, D and E for successive ones of the basic circuits, until the number of connected, operable basic circuits having unique addresses stored therein is equal to the nth power of 2.

Claim 14

A method for fabricating and assembling a block-addressable integrated-circuit store having n address lines and comprising a plurality of basic circuits, each of the basic circuits storing a block of data and including an address identifying means, said method comprising the steps of: A. photographically forming from a corresponding set of master masks of a basic circuit a set of wafer-size masks for manufacturing integrated circuits, the set of master masks including a bus-portion image, wherein the step of forming the wafer-size masks includes the step of repeatedly aligning and abutting the bus-portion image to form a wafer-size input-output bus image; B. forming on a wafer of semiconductor material a group of identical basic circuits including an input-output bus having said n address lines utilizing the set of wafer-size masks formed in the preceding step, the input-output bus electrically interconnecting the group of identical basic circuits each to the other; C. temporarily enabling one of the basic circuits to the input-output bus; D. testing via the input-output bus the temporarily enabled basic circuit for operability; E. disabling the temporarily enabled basic circuit from the input-output bus if the one basic circuit is found defective during the testing step and proceeding to step H, otherwise proceeding to step F; F. storing a unique address in a storage means in the temporarily enabled basic circuit determined operable during the testing step; G. connecting the operable, uniquely addressable basic circuit to the input-output bus; and H. repeating steps C, D and E for successive ones of the basic circuits, until the number of connected, operable basic circuits having unique addresses stored therein is equal to the nth power of 2.

Claim 15

A method for fabricating and assembling a block-addressable integrated-circuit store having n address lines and comprising a plurality of basic circuits, each of the basic circuits storing a block of data and each including an address-identifying means, said method comprising the steps of: A. photographically forming from a corresponding set of master masks of a basic circuit a set of wafer-size masks for manufacturing integrated circuits, the set of master masks including a bus-portion image, wherein the step of forming the set of wafer-size masks includes the step of repeatedly aligning and abutting the bus-portion image to form a wafer-size input-output bus image; B. forming on a wafer of semiconductor material a group of like basic circuits including an input-output bus having said n address lines utilizing the set of wafer-size masks formed in the preceding step, the input-output bus electrically interconnecting the group of like basic circuits each to the other; C. temporarily enabLing one of the basic circuits to the input-output bus; D. testing via the input-output bus the temporarily enabled basic circuit for operability; E. disabling the temporarily enabled basic circuit from the input-output bus if the one basic circuit is found defective during the testing step and proceeding to step H, otherwise proceeding to the next step; F. storing a unique binary address in the address-identifying means of the temporarily enabled basic circuit determined operable during the testing step; G. connecting the operable basic circuit having the unique addresses stored therein to the input-output bus; H. repeating steps C, D and E for successive ones of the basic circuits on the wafer, until substantially all of the operable basic circuits on the wafer are connected to the input-output bus; I. repeating steps B through H for other wafers until the number of connected operable basic circuits having unique addresses stored therein is equal at least to the nth power of 2; and J. electrically interconnecting the input-output busses of the wafer and said other wafers to form a matched-set assembly of wafers having a total number of operable addressable basic circuits equal to the nth power of 2.

Claim 16

A method for fabricating and assembling a block-addressable integrated-circuit store having n address lines and comprising a plurality of basic circuits, each of the basic circuits storing a block of data and each including an address-identifying means, said method comprising the steps of: A. photographically forming from a corresponding set of master masks of a basic circuit a set of wafer-size masks for manufacturing integrated circuits, the set of master masks including a bus-portion image, wherein the step of forming the set of wafer-size masks includes the step of repeatedly aligning and abutting the bus-portion image to form a wafer-size input-output bus image; B. forming on a wafer of semiconductor material a group of like basic circuits including an input-output bus having said n address lines utilizing the set of wafer-size masks formed in the preceding step, the input-output bus electrically interconnecting the group of like basic circuits each to the other; C. temporarily enabLing one of the basic circuits to the input-output bus; D. testing via the input-output bus the temporarily enabled basic circuit for operability; E. disabling the temporarily enabled basic circuit from the input-output bus if the one basic circuit is found defective during the testing step and proceeding to step H, otherwise proceeding to the next step; F. storing a unique binary address in the address-identifying means of the temporarily enabled basic circuit determined operable during the testing step; G. connecting the operable basic circuit having the unique addresses stored therein to the input-output bus; H. repeating steps C, D and E for successive ones of the basic circuits on the wafer, until substantially all of the operable basic circuits on the wafer are connected to the input-output bus; I. repeating steps B through H for other wafers until the number of connected operable basic circuits having unique addresses stored therein is equal at least to the nth power of 2; and J. electrically interconnecting the input-output busses of the wafer and said other wafers to form a matched-set assembly of wafers having a total number of operable addressable basic circuits equal to the nth power of 2.

Claim 17

A method for fabricating and assembling a block-addressable integrated-circuit memory of the type comprising a plurality of identical basic circuits and including a plurality of address lines, each of the basic circuits storing a block of data and each including a binary address-identifying means, said method comprising the steps of: A. photographically forming from a corresponding set of master masks of a basic circuit a set of wafer-size masks for manufacturing integrated circuits, the set of master masks including a bus-portion image, wherein the step of forming the set of wafer-size masks includes the step of repeatedly aligning and abutting the bus-portion image to form a wafer-size input-output bus image; B. forming on a wafer of semiconductor material a group of like basic circuits including an input-output bus having said plurality of address lines utilizing the set of wafer-size masks formed in the preceding step, the input-output bus electrically interconnecting the group of like basic circuits each to the other; C. temporarily enabling one of the basic circuits to the input-output bus; D. testing via the input-output bus the temporarily enabled basic circuit for operability; E. disabling the temporarily enabled basic circuit from the input-output bus if the one basic circuit is found defective during the testing step and proceeding to step H, otherwise proceeding to step F; F. storing a unique address in the address-identifying means of the temporarily enabled basic circuit determined operable during the testing step; G. connecting the operable basic circuit to the input-output bus; H. repeating steps C, D and E for successive ones of the basic circuits, until all of the defective basic circuits on the wafer are disabled and substantially all of the operable circuits on the wafer are connected to the input-output bus, the connected operable basic circuits on the wafer having unique addresses stored therein ranging from zero through the total number of connected operable basic circuits; I. repeating steps B through H for other wafers; J. choosing two wafers having a total number of connected operable basic circuits equal at least to an integer power of two; and K. interconnecting the plurality of address lines of the chosen wafers, each of the address lines of one of the chosen wafers connected through inverters to corresponding ones of the address lines of the other wafer to form a matched-pair assembly of wafers.

Claim 18

A method for fabricating and assembling a block-addressable integrated-circuit memory of the type comprising a plurality of identical basic circuits and including a plurality of address lines, each of the basic circuits storing a block of data and each including a binary address-identifying means, said method comprising the steps of: A. photographically forming from a corresponding set of master masks of a basic circuit a set of wafer-size masks for manufacturing integrated circuits, the set of master masks including a bus-portion image, wherein the step of forming the set of wafer-size masks includes the step of repeatedly aligning and abutting the bus-portion image to form a wafer-size input-output bus image; B. forming on a wafer of semiconductor material a group of like basic circuits including an input-output bus having said plurality of address lines utilizing the set of wafer-size masks formed in the preceding step, the input-output bus electrically interconnecting the group of like basic circuits each to the other; C. temporarily enabling one of the basic circuits to the input-output bus; D. testing via the input-output bus the temporarily enabled basic circuit for operability; E. disabling the temporarily enabled basic circuit from the input-output bus if the one basic circuit is found defective during the testing step and proceeding to step H, otherwise proceeding to step F; F. storing a unique address in the address-identifying means of the temporarily enabled basic circuit determined operable during the testing step; G. connecting the operable basic circuit to the input-output bus; H. repeating steps C, D and E for successive ones of the basic circuits, until all of the defective basic circuits on the wafer are disabled and substantially all of the operable circuits on the wafer are connected to the input-output bus, the connected operable basic circuits on the wafer having unique addresses stored therein ranging from zero through the total number of connected operable basic circuits; I. repeating steps B through H for other wafers; J. choosing two wafers having a total number of connected operable basic circuits equal at least to an integer power of two; and K. interconnecting the plurality of address lines of the chosen wafers, each of the address lines of one of the chosen wafers connected through inverters to corresponding ones of the address lines of the other wafer to form a matched-pair assembly of wafers.